Basic Test Setup
3.3.3
ADS54J54 GUI
Use the following steps for setting up the ADS54J54 GUI:
1. Start the ADS54J54 EVM GUI by selecting
Start Menu
→
Program Files
→
Texas Instruments
ADCs
→
ADS54J54 EVM GUI
.
2. In the upper right-hand corner, there is either a red or green LED indicator labeled
USB Status
and a
button labeled
RECONNECT FTDI?
. If the LED button is red, then click the button until the LED
indicator turns green. This indicates that the ADS54J54EVM is connected to the computer.
3. Under the ADC Controls tab of the ADS54J54 tab, click on the
Reset ADC
button. The ADS54J54
EVM SPI GUI always does a read-back of every register write to verify that the desired value was
written. The ADS54J54 powers up in 3-wire SPI mode while the GUI requires 4-wire mode for the
readback function to work properly. The
Reset ADC
button will reset the ADC and set the device in 4-
wire mode so that the GUI will continue to work properly.
4. Under the PLL1 Controls tab of the LMK04828 tab, click on the
Reset LMK
button. The LMK04828
powers up in 3-wire SPI mode while the GUI requires 4-wire mode for the readback function to work
properly. The
Reset LMK
button will reset the LMK04828 and set the device in 4-wire mode so that
the GUI will continue to work properly.
5. On the low-level tab, click the
Load Config
button. Choose one of the configuration files available. If
choosing ADS54J54_500M_442.cfg, this configuration file will set the ADS54J54 to use four
JESD204B lanes and set up the 2x decimation filter to output 250 Msps while the LMK04828 is
configured to provide a 500-MHz device clock to the ADS54J54. If choosing
ADS54J54_500M_881.cfg, the ADS54J54 will not decimate the sample output to 250 Msps but will
output 500 Msps on 8 JESD204B lanes.
6. The two PLL's of the LMK04828 should now be locked. This is indicated on the ADS54J54 circuit
board by the illuminated LED's, D4 (PLL2 LOCKED) and D1 labeled (LMK LOCKED).
7. The TSW14J56 capture card should now be receiving a DEVICE clock and a SYSREF clock. This
causes the receiver FPGA to assert the JESD204B SYNC high, since synchronization has not been
established with the transmitter ADC. This is indicated by LED D3 (JESD_SYNC) illuminating on the
ADS54J54EVM. The SYSREF signal can be observed on either SMA J4 or J17 of the ADC EVM.
8. The TSW14J56 capture card should now be receiving valid data.
9. Since a periodic SYSREF signal acts as a sub-harmonic clock of the converter sampling clock and
may have spurious effect on the converter performance, it may be turned off during normal operation
once synchronization has been achieved. Click on the tab labeled
LMK0428 Clock Outputs
located at
the top of the GUI. Check the control for SDCLKout_PD in the block of controls for clocks CLKout 2
and 3. (See
) This will power down the SYSREF to the ADS54J54. The SYSREF must be
running initially in order to establish a JESD204B link between the ADS54J54 and the FPGA on the
TSW14J56 but after initialization, the SYSREF is no longer needed and may result in clock spurs
coupling into the ADS54J54, reducing performance.
NOTE:
If SYSREF is turned off during normal operation, TX and RX devices must have the ability to
generate a
Generate SYSREF
request to the LMK04828 clock generator whenever a
synchronization request is detected at the SYNC interface.
10. If the JESD204B link does not get established, make sure the SYSREF MUX panel on the ADS54J54
GUI is set to SYSREF CONTINUOUS. If this is set to any other value, the SYSREF outputs will be
disabled from the LMK04828, thus preventing synchronization from occurring.
16
ADS54J54 Evaluation Module
SLAU616A – January 2015 – Revised January 2016
Copyright © 2015–2016, Texas Instruments Incorporated
