Texas Instruments ADS54J54EVM, Руководство пользователя

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2.2.2 ADC Controls
Clicking on the ADS54J54 tab in Figure 2 takes the user to a bank of tabs for control of the ADS54J54,
one of which is the ADC Controls tab, as shown in Figure 3 . The ADC Controls tab controls various ADC
functions such as the over-range detection, test patterns, output modes, input clocking modes, and power
down controls.
Table 2 describes the controls seen in this window. The higher level tabs remain visible at
all times so that the user may quickly move to controls for the LMK04828 or to low-level register controls.
Figure 3. ADS54J54 Controls Tab
Table 2. ADS54J54 Controls Tab Descriptions
Control Description
Device Reset Resets the ADS54J54 SPI registers and sets the device in 4-wire SPI mode
VREF Voltage Selects the reference voltage and thus, the full scale voltage
Input Clock Divider AB and CD Selects an input divider of /1, /2, or /4 for channels A and B or channels C and D,
respectively
CLK SEL AB and CD Selects the clock input for channels A and B or for channels C and D, respectively
CLK Phase SEL AB and CD Selects the phase relationship of the clock input for channels A and B or for channels C
and D, respectively
CLK SW AB and CD Used in conjunction with changing the clock phase relationship of channels A and B or
channels C and D.
Data Format Selects offset binary or two's complement data format
Decimation Filter EN AB and CD Enables the decimation filter for channels A and B or channels C and D
Decimation Filter AB and CD Selects whether the decimation filter will be high-pass of low-pass
Fast OVR Length AB and CD Selects how long the OVR output is active upon overrange detection
Fast OVR Threshold AB and CD Sets how close to full scale the input can be before the fast overrange will detect
overrange
OVRx OUT EN Selects the function of the fast OVR pin for each of the four channels
6 ADS54J54 Evaluation Module SLAU616A – January 2015 – Revised January 2016
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