TCP201 User Manual Issue 1.4
Page 23 of 35
The TCP201 supports read and write cycles to the IP I/O space.
The TCP201 supports read and write cycles to the IP ID space. A PCI access to the TCP201 will be
terminated in every case. If the IP supports write access to its ID space, data will be written to the ID-
PROM. If the IP does not support write access to its ID space, no ACK# will be generated by the IP to
the local control logic, and a local timeout will terminate the IP write cycle after a timeout time of 8µs
and the timeout bit is set in the IP Status Register.
The TCP201 supports read and write cycles to the IP INT space. A read access to the IP INT space
initiates an IP interrupt acknowledge cycle. A read access with address A1=0 (i.e. 0x0000_00c0)
initiates an interrupt acknowledge cycle for IP INT0#, a read access with address A1=1 (i.e.
0x0000_00C2) initiates an interrupt acknowledge cycle for IP INT1#. The read access returns the
interrupt vector. This feature is helpful for IP modules that require an interrupt acknowledge cycle to
remove their pending interrupt request. If the IP does not support write access to its INT space, no
ACK# will be generated by the IP, and a local timeout will terminate the cycle after a timeout time of
8µs and the timeout bit is set in the IP Status Register.
4.1.3 Local Space 2 Address Map
The PCI9030 local space 2 is used for the IP A-D Memory space (16 bit port). IPs with Memory space
that uses D7:0 only, should be accessed via Local Space 3. See section below for details.
The PCI base address for local space 2 can be obtained from the PCIBAR4 Register at offset 0x20 in
the PCI9030 PCI configuration register space.
PCI Base Address 4 +
Start
End
Size
(Byte)
Description
0x0000_0000
0x007F_FFFF
8M
IP A MEM Space (16 bit)
0x0080_0000
0x00FF_FFFF
8M
IP B MEM Space (16 bit)
0x0100_0000
0x017F_FFFF
8M
IP C MEM Space (16 bit)
0x0180_0000
0x01FF_FFFF
8M
IP D MEM Space (16 bit)
Figure 4-4 : Local Space 2 Address Map (IP A-D Memory Space 16 bit)
