TCP201 User Manual Issue 1.4
Page 15 of 35
3.4 Endian Conventions
This chapter tries to illuminate the mixed use of Big Endian and Little Endian convention in one
system. The major difference between Big Endian and Little Endian are swapped byte lanes. The
byte lanes for 16 bit and 32 bit data busses with Big Endian and Little Endian are shown below:
Little Endian convention on a 16 bit Data Bus:
Byte Lane
Byte 1
Byte 0
Data Line
D15 : D8
D7 : D0 (LSB)
Big Endian convention on a 16 bit Data Bus:
Byte Lane
Byte 0
Byte 1
Data Line
D15 : D8
D7 : D0 (LSB)
Little Endian convention on a 32 bit Data Bus:
Byte Lane
Byte 3
Byte 2
Byte 1
Byte 0
Data Line
D31 : D24
D23 : D16
D15 : D8
D7 : D0 (LSB)
Big Endian convention on a 32 bit Data Bus:
Byte Lane
Byte 0
Byte 1
Byte 2
Byte 3
Data Line
D31 : D24
D23 : D16
D15 : D8
D7 : D0 (LSB)
The PCI Bus and all Intel CPUs work in Little Endian mode. VMEbus, PowerPC and 68K CPUs
work in Big Endian mode. Most IP modules, which are common in VMEbus systems, also use Big
Endian byte ordering.
The TCP201 works in Little Endian mode by default, but can be switched to work in Big Endian
mode. This leads to 4 major Big- Little Endian combinations in one system:
- Little Endian CPU with TCP201 (Little Endian) and IP module (Big Endian)
- Little Endian CPU with TCP201 (Big Endian) and IP module (Big Endian)
- Big Endian CPU with TCP201 (Big Endian) and IP module (Big Endian)
- Big Endian CPU with TCP201 (Little Endian) and IP module (Big Endian)
See the next four subchapters for a detailed view on these combinations.
