TCP201 User Manual Issue 1.4
Page 31 of 35
Bit
Name
Description
4
INT0_C
Read : 0 : No IP_C interrupt 0 request
1 : Active IP_C interrupt 0 request
Write : 0 : No effect
1 : Clear edge sensitive IP_C interrupt 0
status
3
INT1_B
Read : 0 : No IP_B interrupt 1 request
1 : Active IP_B interrupt 1 request
Write : 0 : No effect
1 : Clear edge sensitive IP_B interrupt 1
status
2
INT0_B
Read : 0 : No IP_B interrupt 0 request
1 : Active IP_B interrupt 0 request
Write : 0 : No effect
1 : Clear edge sensitive IP_B interrupt 0
status
1
INT1_A
Read : 0 : No IP_A interrupt 1 request
1 : Active IP_A interrupt 1 request
Write : 0 : No effect
1 : Clear edge sensitive IP_A interrupt 1
status
0 (LSB)
INT0_A
Read : 0 : No IP_A interrupt 0 request
1 : Active IP_A interrupt 0 request
Write : 0 : No effect
1 : Clear edge sensitive IP_A interrupt 0
status
Figure 4-12: IP Status Register (PCI Base Address 2 + 0x0C)
4.3 IP Interrupts
All IP interface interrupt sources (Timeout, Error, IP A-D INT0, IP A-D INT1) are mapped to PCI
interrupt INTA#.
For quick interrupt source detection, the IP Status Register can be read to determine the IP interrupt
source.
Level sensitive IP interrupts, which are most common for IP modules are cleared by either an interrupt
acknowledge cycle to the IP or by accessing an Interrupt Status Register on the IP module.
A read access to the IP INT space initiates an IP interrupt acknowledge cycle. A read access with
address A1=0 (i.e. 0x0000_00c0) initiates an interrupt acknowledge cycle for IP INT0#, a read access
with address A1=1 (i.e. 0x0000_00C2) initiates an interrupt acknowledge cycle for IP INT1#. The read
access returns the interrupt vector. This feature is helpful for IP modules that require an interrupt
acknowledge cycle to remove their pending interrupt request.
Timeout interrupts and edge sensitive IP interrupts must be cleared in the IP Status Register.
IP Error interrupts must be cleared in the corresponding IP Control Register.
