Terasic HAN Pilot Platform, Руководство по демонстрации

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HAN Pilot Platform
Demonstration Manual 12 www.terasic.com
September 6, 2019
Figure 2-11 CDCM6208 Demo
2.3 Nios DDR4 SDRAM Test
Many applications use a high performance RAM, such as a DDR4 SDRAM, to provide temporary
storage. In this demonstration hardware and software designs are provided to illustrate how to
perform DDR4 memory access in QSYS. We describe how the Altera’s “Arria 10 External Memory
Interfaces” IP is used to access the two DDR4-Sodimm on the FPGA board, and how the Nios II
processor is used to read and write the SDRAM for hardware verification. The DDR4 SDRAM
controller handles the complex aspects of using DDR4 SDRAM by initializing the memory devices,
managing SDRAM banks, and keeping the devices refreshed at appropriate intervals.
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System Block Diagram
Figure 2-12 shows the system block diagram of this demonstration. The QSYS system requires one
50 MHz and two 266.667MHz clock source. The two 266.667 MHz clock source is provided by
CDCM6208 clock generator on the board. The 50MHz is used by IO PLL to generate 200MHz for
Nios Processor and On-chip Memory. The two 266.667MHz clock are used as reference clocks for
the DDR4 controllers. There are two DDR4 Controllers are used in the demonstrations. Each
controller is responsible for one DDR4 SDRAM. Each DDR4 controller is configured as a 1 GB
DDR4-1066MHz controller. The DDR4A controllers are designed as 1GB rather 4GB is due to
address space limitation of Nios II processor. Nios II processor is used to perform memory test. The
Nios II program is running in the On-Chip Memory. A PIO Controller is used to monitor buttons
status which is used to trigger starting memory testing.