Terasic HAN Pilot Platform, Руководство по демонстрации

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HAN Pilot Platform
Demonstration Manual 13 www.terasic.com
September 6, 2019
Figure 2-12 Block Diagram of the DDR4 Basic Demonstration
The system flow is controlled by a Nios II program. First, the Nios II program writes test patterns
into the whole 1 GB of SDRAM. Then, it calls Nios II system function (alt_dache_flush_all) to
make sure all data has been written to SDRAM. Finally, it reads data from SDRAM for data
verification. The program will show progress in JTAG-Terminal when writing/reading data to/from
the SDRAM. When verification process is completed, the result is displayed in the JTAG-Terminal.
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Design Tools

Quartus Prime 18.0.0 Standard Edition

Nios II Software Build Tools for Eclipse 18.0
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Demonstration Source Code
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Quartus Project directory: NIOS_DDR4
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Nios II Eclipse: NIOS_DDR4 \software
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Nios II Project Compilation

Nios II Project Compilation
Before you attempt to compile the reference design under Nios II Eclipse, make sure the project is
cleaned first by clicking ‘Clean’ from the ‘Project’ menu of Nios II Eclipse.

Demonstration Batch File
Demo Batch File Folder: NIOS_DDR4 \demo_batch
The demo batch file includes following files:

Batch File for USB-Blaster II: test.bat, test.sh
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FPGA Configure File: NIOS_DDR4.sof