Terasic HAN Pilot Platform, Руководство по демонстрации

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HAN Pilot Platform
Demonstration Manual 35 www.terasic.com
September 6, 2019
Figure 2-34 QSYS for Ethernet Simple Socket Server
In the Triple-Speed Ethernet IP Core configuration, the interface is set to SGMII as well as using
the internal FIFO shown in
Figure 2-35 .
Figure 2-35 Triple-Speed Ethernet core configurations
In the MAC options section, the MDIO module is included that controls the PHY Management
Module associated with the MAC block. The host clock divisor is to divide the MAC control
register interface clock to produce the MDC clock output on the MDIO interface. The MAC control
register interface clock frequency is 100 MHz and the desired MDC clock frequency is 2.5 MHz, a
host clock divisor of 40 should be used. Once the Triple-Speed Ethernet IP configuration has been
set and necessary hardware connections has been made click on ‘Generate’ to build the interconnect