Terasic HAN Pilot Platform, Руководство по демонстрации

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HAN Pilot Platform
Demonstration Manual 63 www.terasic.com
September 6, 2019
HPS-to-FPGA bridge is mastered by the L3 slave peripheral switch.
The FPGA-to-HPS bridge masters the L3 main switch, allowing any master implemented in the
FPGA fabric to access most slaves in the HPS. For example, the FPGA-to-HPS bridge can access
the accelerator coherency.
All three bridges contain global programmer view GPV register. The GPV register control the
behavior of the bridge. It is able to access to the GPV registers of all three bridges through the
lightweight HPS-to-FPGA bridge.
This Demo introduces to users how to use the HPS/ARM to communicate with FPGA. This project
includes GHRD project for the HAN Pilot Platform one ARM C Project which demonstrates how
HPS/ARM program controls the LEDs connected to FPGA.
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The term GHRD is short for Golden Hardware Reference Design. The GRD project provide by
Terasic for the HAN Pilot Platform is located in the CD folder: CD-ROM\ Demonstration\
SOC_FPGA\ a10s_ghrd.
The project consists of the following components:

ARM Cortex™-A9 MP Core HPS

Two user push-button inputs

Two user DIP switch inputs

Two user I/O for LED outputs

256 KB of on-chip memory

JTAG to Avalon master bridges

Interrupt capturer for use with System Console

System ID
The memory map of system peripherals in the FPGA portion of the SoC as viewed by the MPU
starts at the lightweight HPS-to-FPGA base address 0xFF20_0000. The MPU can access these
peripherals through the Address offset setting in the Qsys. User can open the GHRD project with
Quartus Software. Then open the a10s_ghrd.qsys file with the Qsys tool.
Figure 4-2 lists the
address map of the peripherals which are connected to the lightweight HPS-to-FPGA.
Figure 4-2 FPGA peripherals address map
All the Avalon Conduit signals of these peripherals are connected to the I/O pins of the SoC FPGA
on HAN Pilot Platform as shown in the
Figure 4-3 .