Terasic HAN Pilot Platform, Руководство по демонстрации

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HAN Pilot Platform
Demonstration Manual 105 www.terasic.com
September 6, 2019
PCIE_BAR4, in respectively. The on-chip memory base address is 0x00000000 relative to the
DMA controller.
Before accessing the FPGA through PCI Express, the application first calls PCIE_Load to
dynamically load the TERASIC_PCIE_AVMM.dll. Then, it calls PCIE_Open to open the PCI
Express driver. The constant DEFAULT_PCIE_VID and DEFAULT_PCIE_DID used in
PCIE_Open are defined in TERASIC_PCIE_AVMM.h. If developer change the Vendor ID and
Device ID and PCI Express IP, they also need to change the ID value define in
TERASIC_PCIE_AVMM.h. If the return value of PCIE_Open is zero, it means the driver cannot be
accessed successfully. In this case, please make sure:

The FPGA is configured with the associated bit-stream file and the host is rebooted.

The PCI express driver is loaded successfully.
The LED control is implemented by calling PCIE_Write32 API, as shown below:
The button status query is implemented by calling the PCIE_Read32 API, as shown below:
The memory-mapped memory read and write test is implemented by PCIE_DmaWrite and
PCIE_DmaRead API, as shown below:
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The application reference design shows how to add DDR4 Memory Controllers for DDR4-A
SODIMM and on board DDR4-B into the PCIe Quartus project based on the PCIe_Fundamental
Quartus project and perform 4GB data DMA for both SODIMM. Also, this demo shows how to call
“PCIE_ConfigRead32” API to check PCIe link status.

Demonstration Files Location
The demo file is located in the batch folder:
CDROM\ Demonstrations\PCIe_DDR4\demo_batch
The folder includes following files:

FPGA Configuration File: PCIe_DDR4.sof

Download Batch file: test.sh

Linux Application Software folder: linux_app, includes

PCIE_DDR4