Terasic DE10-Agiles, Руководство пользователя

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DE10-Agilex
User Manual 27 www.terasic.com
January 29,
2021
Figure 2-15 Clock circuit of the FPGA Board
A clock buffer (Si53306) is used to duplicate the 50 MHz TCXO output clock, so there
are three 50MHz clocks fed into different Agilex FPGA banks and one clock for USB
blaster II circuit. The programming clock generator (Si5340A) with low-jitter clock
output which are used to provide special and high- quality clock signals for high-speed
transceivers. Through I2C serial interface, the clock generator controllers in the Agilex
FPGA can be used to program the Si5340As to generate many frequencies to each
QSFP-DD port.
For memory interface, the board provide a dual frequency OSC (166.667M and 300
MHz) and fan out it to four different clocks to the Agilex FPGA via clock buffer
(Si53306). The four clocks are used for the reference clock of the four DDR4
SODIMMs. Users can adjust SW5 to change the OSC output frequency according to
their application needs .For details, please refer to th e " DDR4 Clock Source Switch "
part of section 2.3 .
Two UFL connectors provide two external single-ended clock inputs or one external
differential clock inputs. One oscillator provides a 125 MHz clock used as configuration
clock or used as the clock for transceiver calibration. Besides, there is one 100 MHz
clock source to use as the FPGA input clock.