Terasic DE10-Agiles, Руководство пользователя

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DE10-Agilex
User Manual 21 www.terasic.com
January 29,
2021
Figure 2-10 FACTORY position of slide switch SW6 for Image Select
– Factory
Image Load

DDR4 Clock Source Switch
Figure 2-11 is the DDR4 reference clock diagram on the DE10-Agilex board. A dual
frequency OSC that can provide two frequencies to a 1:4 clock buffer, then it will be fan
out to four of differential clock pairs to the FPGA. These four pair of clocks used as
reference clocks for four DDR4 SODIMMs. Users can use SW5 (See Figure 2-12 ) to
switch the output frequency of OSC to provide 166.667Mhz or 300Mhz clock to FPGA.
This allows users to have more DDR4 reference clock frequencies options for
applications.
Figure 2-11 The DDR4 reference clock diagram