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S50 Hardware User Guide
1VV0301505 Rev. 3
Page 20 of 60
2021-05-05
Not Subject to NDA
VDDIO
(+1.2V .. +3.6V)
S50
GND
D-2
F-4
F-3
D-7
UART_RXD
UART_TXD
UART_CTS#
UART_RTS#
10µ+100n+1n
SN74AVC4T245
User Host System
VSUP
XC6209F-3.3
VOUT
VSS
VIN
CE
1µ
10
0k
100k
VCCB
1B1
1B2
2B1
2B2
2A2
2A1
1A2
1A1
VCCA
1DIR
1OE
2DIR
2OE
(GPIO, Out,
no pu/pd)
(GPIO, Out,
no pu/pd)
TXD
RTS#
RXD
CTS#
+5VDC
OE_DRV#
BT_ENABLE
VDD_HOST (+1.2 .. +3.6V)
+3V3_switched
Figure 10: S50 Example Serial Interface (Mixed Signal Level)
4.4.
General Purpose I/O (GPIO)
Functionality is defined project specific in the firmware used.
It is possible to use the programmable digital I/Os GPIO[0:14] on the S50.
Unused GPIO pins shall be left unconnected to stay compatible. There may be functions
assigned to some in future versions of the firmware. Refer to 5.3
4.5.
I
2
C Interface
Functionality is defined project specific in the firmware used.
The I
2
C bus interface serves as an interface between the internal microcontroller and the
serial I
2
C bus. S50 is the master and controls all I
2
C bus specific sequencing,
protocol, and timing. It supports standard (100kHz) and fast (400kHz) speed modes. The
S50 as an I
2
C master must be the only master of the I
2
C bus (no multimaster
capability). Clock stretching is supported.
SDA and SCL can be used to form an I
2
C interface. It is required to connect 4k7 pull-up
resistors on SCL and SDA when this interface is used.
I2C-SCL
I2C-SDA
GPIO[0]/I2C-SCL
GPIO[1]/I2C-SDA
S50
Rpu
VSUP
B-2
D-3
Rpu
VSUP
4k
7
4k
7
Figure 11: S50 I
2
C Interface
Содержание BlueMod+S50
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