Theory of Operation—2246 1Y and 2246 Mod A Service
Table 3-15
Display Sequencer Channel Select Logic Bits
RD5
RD4
RD3
Channel
0
0
0
CH 1
0
0
1
CH 2
0
1
0
CH 1 + CH 2
0
1
1
CH 3
1
0
0
CH 4
Bit RD2 selects between the A Sweep display and
the B Sweep display (only used in ALT Vertical Mode
(with m easurem ent). The A Sweep is displayed if
this bit is set high (outputs HD1, HDO = 01), other
wise the B Sweep is displayed (outputs HD1,
HDO = 1 0 ) . Bit RD1 controls the DS (delay select)
output pin in ALT Vertical Mode (with or without
m easurem ent). Finally, bit RDO marks the last state
in a display sequence. When the RDO bit goes high,
the sequencer finishes its current state and jumps
back to the initial state (RAM address 000 is the
initial state). In ALT Vertical Mode, the sequencer
will advance to the next state either on each rising
edge of the trigger holdoff pulse (ALT Vertical Mode
with m easurem ent), or on every other rising edge of
the trigger holdoff pulse (ALT Vertical Mode with no
m easurem ent).
The first type of ALT Mode is used when there is an
intensified zone (with or without an accompanying
B Sweep) for only one or two of the displayed
channel (s); every display state can be completely
specified by programming the RAM properly (no
more than eight display states are ever needed for
any measurement display sequence; hence, the
RAM is limited to eight addresses). The second type
of ALT Mode is used when there are intensified
zones and B Sweeps for all channels displayed. In
this mode, HD1 and HDO automatically alternate
between the A sweep and the B Sweep on each
rising edge of the trigger holdoff pulse. Whenever
HD1 and HDO switch from the B Sweep back to the A
Sweep, the vertical sequencer advances to its next
state. This second type of ALT Vertical Mode is used
only when more than eight RAM locations are
needed to define a long display sequence in ALT
Horizontal Mode.
In ALT Vertical Mode, the vertical and horizontal dis
play enable outputs are initialized as follows: the
trigger holdoff output is forced high (via the
processor interface), RESET is strobed, then trigger
holdoff is unforced to allow sweeps to occur. This
procedure ensures that the display enable and trig
ger source outputs are initialized to the first state of
the programmed display sequence.
In CHOP Vertical Mode, the leading edge of the chop
blanking pulses advance the vertical display enable
outputs. RAM bits RD5, RD4, and RD3 still determine
the vertical channel displayed, and RAM bit RDO
marks the last display state in the sequence. RAM
bits RD2, and RD1 are not used in CHOP Mode.
Other circuitry, clocked by the trigger holdoff pulse,
drives the horizontal display control outputs. The
same initialization procedure as described above for
ALT Vertical Mode is used. However, only the trigger
source and horizontal display enable outputs are
initialized. The vertical-display-enable outputs cycle
at the CHOP rate. Table 3-16 specifies the behavior
of the horizontal- display-enable outputs for all hori
zontal and vertical modes.
Trigger Holdoff Timer
When the B ENDS A control bit is low, the holdoff
tim er is triggered by the rising edge of A GATE.
When the B ENDS A control bit is high, the holdoff
tim er is triggered by either the rising edge of
B GATE, or the rising edge of A GATE, whichever
occurs first. The THO output pin will go high
immediately, and go low after the programmed
number of holdoff oscillator cycles. In SGL SEQ
Mode (again, with the TEST input pin high), the
EOSS (end of single sequence) flag will go high and
the THO output will stay high after the last A Sweep
of the programmed sequence. Strobing RESET will
reset the EOSS flag, and set the THO output back
low again, if THO hasn’t been forced high via the
Measurement Processor interface.
HOLDOFF OSCILLATOR. A relaxation oscillator circuit
formed by U601, Q600, Q601 and associated com
ponents is connected between the OSC OUT and
OSC RST pins to provide the input count pulses to
the holdoff tim er. The HOLDOFF voltage applied to
the base of Q600 sets up a charging current into
timing capacitor C600. When the holdoff timer is
inactive, the OSC RST output pin is high, and C600 is
held discharged. With the capacitor discharged, the
output of the oscillator is held high. When a rising
edge of A GATE (or B GATE in B ends A mode)
occurs, the OSC RST output will go low and allow the
voltage across C600 to ramp up. When this voltage
crosses an upper threshold, the output of U601 at
pin 7 goes low. This negative transition increments
the internal holdoff counter, and causes the OSC
RST output to go high, again discharging C600.
When the voltage drops below a lower threshold, the
oscillator output again goes high to repeat the oscil
lation cycle. After the last negative transition on the
OSC OUT pin for a particular count length, the OSC
RST output will go high and stay there until the next
time the THO tim er is triggered.
3-23
Содержание 2246 1Y
Страница 13: ...2246A Service 7062 01 X The 2246 1Y or 2246 Mod A Portable Oscilloscope ...
Страница 35: ......
Страница 69: ...Theory of Operation 2246 1Y and 2246 Mod A Service 15 V 6081 07 3 32 Figure 3 4 Simplified Sweep Circuit ...
Страница 91: ...Theory of Operation 2246 1Y and 2246 Mod A Service 6081 12 6557 99 3 54 Figure 3 9 Power Supply block diagram ...
Страница 139: ......
Страница 185: ......
Страница 187: ......
Страница 278: ...Figure 9 5b Detailed 2246 1Y or 2246 Mod A block diagram part 2 R E ...
Страница 287: ......
Страница 304: ...A D D J U N 1991 ...
Страница 311: ...2246 1Y and 2246 Mod A Service WAVEFORMS FOR DIAGRAM 1 0 V r l III B f e I l i 6555 39 ...
Страница 314: ...15 14 13 12 11 10 9 8 7 6 5 12 11 10 9 8 7 AT117 A TI 271 1 2 3 4 5 6 6555 70 Figure 9 8 Hybrid pin identifiers ...
Страница 319: ......
Страница 320: ......
Страница 321: ...2246 1Y and 2246 Mod A Service WAVEFORMS FOR DIAGRAM 2 SET READOUT CONTROL CCW OFF 6555 40 ...
Страница 323: ......
Страница 324: ......
Страница 326: ...A B C P E F G ...
Страница 327: ......
Страница 331: ......
Страница 337: ......
Страница 340: ......
Страница 343: ...C l rti ...
Страница 344: ...WAVEFORMS FOR DIAGRAM 5 2246 1Y and 2246 Mod A Service HORIZ MODE A A SEC DIV 2M S HOLDOFF MIN CCW ...
Страница 345: ...HORIZ MODE ALT A SEC DIV 2M s B SEC DIV 5 mS HOLDOFF MIN DELAY INTENSIFIED ZONE STARTS MIDSCREEN ...
Страница 347: ...BEV JUNE 1991 7062 18 ...
Страница 349: ...2246 1Y and 2246 Mod A Service WAVEFORMS FOR DIAGRAM 6 6555 43 I ...
Страница 354: ...A L B i C 1 D 1 E i F i G 1 2 3 4 5 6 7 8 2246 1Y AND 2246 MOD A _________A fc A A REV JUNE 1991 7062 19 ...
Страница 355: ...I BOARD LOCATION 8K 8J 8H 7H 8H 8H 7J 8D 7H 8H 8J 8J 7K 8K 10D 6L 6K 6L 6K 6G 5H I ...
Страница 362: ......
Страница 372: ...2246 1Y and 2246 Mod A Service WAVEFORMS FOR DIAGRAM 9 MORE ...
Страница 373: ... 6555 72 6557 88 ...
Страница 375: ......
Страница 376: ...SCHEM LOCATION BOARD LOCATION 2E 2B 7F 4B 4J 5D 3J 5C 4L 6D 3L 6C 5L 7D 3L 7D 3M 7D 5M 7D IB 1A 1C 1A 2B 1A 3B 1A ...
Страница 380: ...WAVEFORMS FOR DIAGRAM 10 ...
Страница 387: ...WAVEFORMS FOR DIAGRAM 11 6555 73 6557 48 ...
Страница 394: ...WAVEFORMS FOR DIAGRAM 12 2246 1Y and 2246 Mod A Service i f I S 1 f c i 4 i ...
Страница 395: ...WAVEFORMS FOR DIAGRAM 12 cont 2246 1Y and 2246 Mod A Service ...
Страница 397: ......
Страница 398: ......
Страница 400: ...REV JUNE 1991 7062 39 ...
Страница 401: ......
Страница 403: ......
Страница 404: ......
Страница 406: ...B 2246 IV AND 2246 MOD A ...
Страница 407: ......
Страница 408: ......
Страница 414: ... _ 5 ...
Страница 415: ...2246 1Y 2246 MOD A ...
Страница 416: ......
Страница 423: ...2246 1Y 2246 MOD A ...
Страница 424: ...2246 1Y 2246 MOD A ...
Страница 425: ......
Страница 433: ......