Tektronix 2246 1Y, Руководство по обслуживанию

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Theory of Operation—2246 1Y and 2246 Mod A Service
When the trigger signal level crosses the com ­
parator threshold set by the Trigger LEVEL and
SLOPE control settings, the comparator output
changes states. That state change is applied to the
Trigger Logic 1C (U602, Diagram 4). The Trigger
Logic circuitry then produces the gating that starts
the A or B Sweep as appropriate.
Separate A and B Trigger bandwidth limit circuits
before the Trigger Level Comparators allow the flexi­
bility that is needed for using the B Trigger circuitry
as the measurement signal channel. Even when the
B Trigger signal itself is bandwidth limited, full
bandwidth is used for making measurements.
Signals are measured by using the B Trigger Level
Comparator as a successive-approximation analog-
to-digital converter to determine the peaks or dc
level of the applied signal. When making a measure­
ment, the B Trigger Level signal is driven in a binary
search by the Measurement Processor (via the DAC
system, Diagram 9) while the output of the B Trigger
Level Comparator is monitored. When the smallest
resolution output of the DAC system causes the
comparator output to change states, the Measure­
ment Processor stops the search and uses the DAC
input value at that point as the measured value of
the applied signal.
Video signal processing to obtain either Field or Line
triggering is done in the TV Trigger Detector. Peak
detectors determine the negative or positive peaks
of the applied video signal. Those levels set the
voltage at the reference input of the video signal
comparator at a level that strips off all the video
information (when the slope selection is correct for
the polarity of the applied signal). The remaining
composite sync signal is applied directly to the trig­
ger system for Line triggering. Field triggering is
obtained by filtering the composite sync to obtain
only the vertical sync pulse.
The operating modes of the Trigger circuitry are
controlled by the Measurement Processor. Auxiliary
Data Shift Register U1103 (the last device in shift
register 1) is serially loaded with control bits from
the SR DATA line by the SRI TTL clock. The state
(high or low) of the control bits select the bandwidth
setting of the A and B Triggers, TV LINE or TV FIELD
triggering for the A Trigger system, and either the
TV FIELD signal or the average DC voltage of the
measurement channel for the B Trigger system.
Additional control bits output from the Auxiliary Data
Shift Register are the MAG signal (X I0 Magnification
on or o ff) , X -Y signal (X-Y or Y-T displays), and the
VERT COMP ENABLEsignal (when vertical SELF CAL
is done).
The average dc voltage of a signal being measured
is found by filtering all the ac signal components
from the measurement channel signal. That dc level
is then applied to the B Trigger Level Comparator
where its value is determined by successive approxi­
mation as described earlier.
DISPLAY AND TRIGGER LOGIC AND
PROCESSOR INTERFACE (Diagram 4)
Control of the display states and the trigger system
is done by two special devices. The Display Logic 1C
(U600, also know as SLIC or slow-logic 1C) controls
activities that enable the vertical channels for display
and select the A and B Trigger System operating
states. The Trigger Logic 1C (U602, also known as
FLIC or fast-logic 1C) monitors the A and B Trigger
signals, the A and B SWP END signals, the DLY END
0 and DLY END 1 signals, and controlling signals
from the Display Logic 1C. It outputs the A and B
GATE and the Z-Axis signals that start the sweeps
and unblank the crt at the appropriate times.
Setup data to the internal registers of the two logic
devices is sent from the Measurement Processor
over the MB DATA line. A register is enabled for
loading by the address that is latched on the
ADDR0-ADDR3 lines (from Diagram 8). Data bits are
written to U600 with the SLIC WR strobe, and to
U602 with the FLIC WR strobe. The contents of the
internal registers of the Display Logic 1C may also be
read by the Measurement Processor using the
SLIC RD strobe.
The Processor Interface portion of Diagram 4 han­
dles the serial communications between the serial
shift registers and the Measurement Processor. This
circuitry is the Measurement Processor’ s means of
controlling the circuit hardware setups in response
to a front panel control setting. Data controlling the
state of the serial data bit to be loaded into the shift
registers is placed on the ADDR0-ADDR2 bus lines.
That address is decoded to produce either a high or
a low that is latched on the SR DATA signal line. The
appropriate shift register clock is then generated to
load the latched bit. Each bit is loaded in succession
until all the control bits of a shift register are loaded.
The purpose of shift register (U502) is to permit the
Measurement Processor to read back the outputs of
the shift registers for diagnostic purposes and the
output of the Vertical Comparator during vertical
SELF CAL. The last bit from shift register 0 and shift
register 1 ( RO FREEZE and BW LIMIT respectively)
and the Vertical Comparator (VERT COMP) state are
loaded in parallel and serially shifted out onto the MB
RETURN line to be read by the Measurement
Processor.
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