Theory of Operation
5–10
1710J-Series Waveform Monitors
horizontal sync. With the exception of composite sync, from the sync stripper on
Diagram 1, all inputs the U735 are from the microcontroller on Diagram 5.
Table 5–1 describes the signals output by the timing state machine.
Table 5–1: Timing State Machine Outputs
Signal Name
Function
H TRIG
Triggers signal that synchronizes the line sweep generator when composite
sync signal is available. (To Diagram 4)
V TRIG
Trigger signal that synchronizes the field sweep generator when composite
sync is available. (To Diagram 4)
FLAT
Closes a switch in the filter selection matrix when pulled low. (To Diagram 1)
LPASS
Closes a switch in the filter selection matrix when pulled low. (To Diagram 1)
CH B
Input switch control: CH A when high and CH B when low. (To Diagram 1)
SYNC SIG
A sync signal that is phased to composite sync that is used as the sync
generator synchronizing signal. (To Diagram 4)
Composite sync (SYNSIG) from U735 drives a non-retriggerable one shot,
U844B, that triggers on the leading edges of horizontal sync pulses. The pulse
width is wide enough to lock out half lines from the vertical interval. The output
of U844B are regenerate sync pulses, HSYNC and HSYNC. HSYNC is a clock
source for the PAL and drives the back porch one shot, U844A. The pulse width
is set to end at the start of the burst on the back porch of the composite sync
signal.
The back porch pulse for the DC restorer is generated by U844A and Q737.
C843 and R837 set the position of the pulse. C848 and R849 determine the pulse
width. The RC network, formed by R963, C964, C97, and R964 turns the output
of U844A into a pulse that drives Q99. The voltage follower formed by Q99 and
R98 outputs the BACKPORCH pulse used by the clamp circuits to sample the
composite signal during the backporch. During the vertical interval broad pulses
there is no burst or backporch and therefore no pulse is desired. During the
vertical broad pulses the SYNCSIG from U735 asynchronously clears U844A.
When the dual filter operating mode is selected (lowpass and flat) the filter
inputs (Diagram 1) are switched, which generates a switching glitch during sync
time. HSYNC, from U844B, and the GLITBLKEN are anded to form the
GLITCH BLK signal for the Z-axis circuit to turn off the CRT beam during this
switching transient. When the Q output of U844B goes low, during horizontal
sync, U234D inverts it and inputs it to one input of U234B. If the dual filter
mode is operating, GLITBLKEN (from the microcontroller on Diagram 5) is
high and U234B outputs GLITCH BLK. R003 sets the pulse output amplitude.
Horizontal Sync Generator
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