Teknor Industrial Computers PCI-934, Техническое справочное руководство

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PCI-934 Technical Reference Manual
13-8
CHIPSET FEATURES SETUP (Continued)
Option BIOS
Default
Setup
Default
Possible
Settings
Description
Peer Concurrency En. En. En. ; Dis. Peer concurrency means that more than one PCI device can be
active at a time.
Chipset Special
Features Dis. En. En. ; Dis. When Disabled, the chipset behaves as if it were the earlier Intel
82430FX chipset.
DRAM ECC/PARITY
Select Parity Parity ECC ; Parity Set this option according to the type of DRAM installed in your
system: error-correcting code (ECC) or parity (default).
Memory Parity/ECC
Check Auto Auto En. ; Dis. ;
Auto
In Auto mode, the BIOS enables memory checking automatically
when it detects the presence of ECC or parity DRAM.
Single Bit Error Report En. En. En. ; Dis. If ECC is enabled, selecting Enabled here tells the system to report
an error (NMI) when a correctable single-bit error occurs.
When disabled, a single-bit error will be corrected but not reported.
Use this option if your operating system does not support ECC error
scrubing.
L2 Cache Cacheable
Size 64MB 64MB 64MB ; 512MB Select 512MB only if your system RAM is greater than 64MB.
Chipset NA
#
Asserted
En. En. En. ; Dis. Selecting Enabled allows pipelining, in which the chipset signals the
CPU for a new memory address before all data transfers for the
current cycle are complete, resulting in faster performance.
Pipeline Cache Timing Faster Faster Faster ;
Fastest For a secondary cache of 256KB (one bank), select Faster. For a
secondary cache of 512KB (two banks), select Fast (3-1-1-1, 2-1-1-
1) or Fastest (3-1-1-1, 1-1-1-1). Cache timing 3-1-1-1 is at the CPU
access speed. It requires special SRAMs because the 3-1-1-1 timing
is at the CPU clock rate.
Passive Release En. En. En. ; Dis. Select Enabled, to allow CPU to PCI bus accesses during passive
release otherwise the arbiter only accepts another PCI master
access to local DRAM.
Delayed Transaction Dis. Dis. En. ; Dis. The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with
PCI version 2.1.
Memory Hole Location None None
512K-640K ;
15M-16M ;
None
You can reserve this area of system memory for ISA adapter ROM.
When this area is reserved, it cannot be cached. The user
information of peripherals that need to use this area of system
memory usually discusses their memory requirements.
Supervisor I/O Base
Addr. 190h 190h 190h ; 290h ;
390h
This parameter must reflect the jumper settings for TEKNOR I/O
Base Port.