5-6
SCSI Controller
NCR53C9X SCSI Controller
Bit 1
Selected with ATN
Bit 0
Selected
Configuration
Registers
The CON1, CON2 and CON3 registers allow various operating modes to
be set up. CON1 is used to control the slow cable mode, parity enable and
test, and the 3-bit SCSI host ID. CON2 provides control of the Tagged
queuing, group 2 command and parity control facilities provided by the
53C90A.
Transfer Count
Registers
These combine into a 24-bit counter used by a DMA command, and by the
Command Sequencer to count the decoded length of a received SCSI
command.
FIFO / Flags Register
The FIFO is a 16 byte deep buffer between the SCSI bus and the system
memory accessible to the host via the FIFO Register.
The FIFO Flags register is a read only register which indicates the number
of bytes remaining in the FIFO.
Select / Reconnect
Register
This is a 3-bit wide write only register used to specify the destination SCSI
bus ID for a select or reselect command.
Clock Conversion
Factor Register
This register specifies the clock conversion factor allowing the FSC to be
clocked at different speeds. On the SPARCbook 3, the FSC is clocked at 40
MHz and this register should be loaded with the value 0x00.
Select / Reconnect
Timeout Register
This register specifies the time period to wait for a select / reselect response.
Synchronous Transfer
Period Register
The Transfer Period register is a 5-bit write-only register that specifies the
minimum time between leading edges of successive REQ or ACK pulses.
The default time is 5 clock cycles, the maximum is 35 cycles.
Sequence Step
Register
This provides an incrementing 3-bit sequence count to indicate which steps
of a command sequence have been executed prior to an error or interrupt
condition.
S3GX_TRMBook Page 6 Friday, September 19, 1997 11:39 am
Содержание SPARCbook 3 series
Страница 1: ...Series Technical Reference Manual 980327 02 3 S3GX_TRMBook Page i Friday September 19 1997 11 39 am...
Страница 8: ...viii S3GX_TRMBook Page viii Friday September 19 1997 11 39 am...
Страница 28: ...1 16 Architecture Overview Microcontroller Subsystem S3GX_TRMBook Page 16 Friday September 19 1997 11 39 am...
Страница 44: ...2 16 The SPARC CPU SBus Controller S3GX_TRMBook Page 16 Friday September 19 1997 11 39 am...
Страница 76: ...5 8 SCSI Controller DMA Support S3GX_TRMBook Page 8 Friday September 19 1997 11 39 am...
Страница 82: ...6 6 Ethernet Interface DMA Support for Network Operations S3GX_TRMBook Page 6 Friday September 19 1997 11 39 am...
Страница 96: ...7 14 PCMCIA Interface Microcontroller Registers S3GX_TRMBook Page 14 Friday September 19 1997 11 39 am...
Страница 146: ...9 28 MODEM Class 2 Fax Command Set S3GX_TRMBook Page 28 Friday September 19 1997 11 39 am...
Страница 180: ...11 30 Display Interface RAMDAC S3GX_TRMBook Page 30 Friday September 19 1997 11 39 am...
Страница 210: ...B 10 Connector Information Removable Hard Drive SCSI Connector S3GX_TRMBook Page 10 Friday September 19 1997 11 39 am...
Страница 216: ...Index vi S3GX_TRMBook Page vi Friday September 19 1997 11 39 am...