Tadpole SPARCbook 3 series, Справочное руководство

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2-8
The SPARC CPU
Cache Controller and Memory Management Unit
2.3.1 Floating Point Registers
The FPU contains thirty-two 32-bit floating-point f registers, as illustrated
in Figure
3-8. These form a 32x32-bit register file. The contents of these
registers are transferred to and from external memory under control of the
IU using floating-point load/store instructions. Addresses and control
signals for data accesses during a floating-point load or store are supplied
by the IU, while the FPU supplies or receives the data.
Although the FPU operates concurrently with the IU, a program containing
floating-point computations generates results as if the instructions were
being executed sequentially.
A single f register is able to store one single-precision operand. Two
registers are required to hold a double precision operand.
2.4 Cache Controller and Memory Management Unit
The SPARC’s integral Memory Management Unit (MMU) provides virtual
to physical address translation, memory protection and arbitration between
I/O, data cache and TLB references to physical memory.
Figure 2-3 f Registers
f31
f30
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•
•
•
•
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f01
f00
S3GX_TRMBook Page 8 Friday, September 19, 1997 11:39 am