Tadpole SPARCbook 3 series, Справочное руководство

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2-14
The SPARC CPU
Memory Interface
2.5 Memory Interface
The SPARC provides a 64-bit memory interface which supports up to
128Mbytes of system memory. The memory is composed of four banks of
up to 32Mbytes each. Different density devices are supported, allowing the
SPARCbook 3 to be fitted with a range of memory size options.
The SPARC’s memory interface provides a 64-bit data bus with 2-bit parity
(1 bit parity for each 32 bit word). The memory interface incorporates a
DRAM refresh controller.
The minimum memory access width is 32 bits; 8-bit and 16-bit write
accesses require read-modify-write operation and correct 32-bit boundary
alignment.
2.6 Instruction Cache
The integral instruction cache is a 16Kbyte physically tagged cache. The
instruction cache is organized as 512 lines of 32 bytes each.
2.7 Data Cache
The data cache is a 8Kbyte direct mapped physically tagged write through
cache with no write allocate. It is organized as 512 lines of 16 bytes each.
Data cache read and write hits take no extra pipe cycles, except for
doubleword operations. There are two store buffers which hold data being
stored from the IU or FPU to memory or other physical devices. The store
buffers are 32-bit registers.
2.8 SBus Controller
The SPARC incorporates an SBus Controller which provides a master and
slave interface used to access I/O devices. It connects the CPU core directly
to the SBus and allows DMA devices to access the main DRAM located on
the SPARC’s memory bus. The SBus controller provides 32-bit data,
SBD(31:00), and 28-bit physical address, SBA(27:00), interface to other
devices in SPARCbook 3. The SBus controller also provides five SBus
Slave Select lines, SBSEL(4:0).
S3GX_TRMBook Page 14 Friday, September 19, 1997 11:39 am