Tadpole SPARCbook 3 series, Справочное руководство

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Memory Map and Interrupts
3-3
Address Map
The map for SBus Slot 4 is as shwon in Table 3-2.
The MACIO provides processor accessible control ports for DMA related
operations, for parallel port operations, for SCSI operations and for
network interface control.
The function and access sizes of these locations are discussed in the
relevant chapter for each interface.
The SLAVIO contains a number of internal devices. These are a floppy
controller (not used in SPARCbook 3), two serial controllers (SCCs),
counter/timers and an interrupt controller. The SLAVIO also supports
access to external devices via the EBus.
The internal interface devices each present an independent interface to the
host. Details of these control interfaces are provided in the relevant chapter
for each interface.
Within their assigned spaces in the SLAVIO’s address space, the
RTC/NVRAM and Boot PROM are mapped repeatedly. In the case of the
RTC/NVRAM this means that there are 256 images.
The SLAVIO memory map is shown in Table 3-4.
Address Range
(Hexadecimal)
Resource
Size
(Mbytes)
78000000 7FFFFFFF MACIO 128
70000000 77FFFFFF SLAVIO 128
Table 3-2 SBus Slot 4 Memory Map
Base Address
(Hexadecimal)
Port
7C800000 Parallel Port Registers
78C00000 Network Controller Registers
78800000 SCSI Registers
78400000 DMA Control and Test Registers
78000000 Internal ID Register
Table 3-3 MACIO Port Locations
S3GX_TRMBook Page 3 Friday, September 19, 1997 11:39 am