Tadpole SPARCbook 3 series, Справочное руководство

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Display Interface
11-15
Power 9100 User Interface Controller
11.2.8 VRAM control registers
The VRAM control registers specify the timing and chip configuration of
the P9100 VRAM interface. These are summarized below:
11.2.9 Parameter engine registers
The parameter engine registers include the Device Coordinate registers,
Status Register and Control and Condition register.
Device Coordinate
Registers
The Device Coordinate registers supply the screen coordinates for a
drawing operation. Coordinates can be absolute or reltaiveto the window
offset. Located at base address 0x38003000, there are four X and four Y
registers each for absolute and relative coordinates. These are summarized
below in Table 11-7.
Address Register Function
38000184 Memory Configuration This read-write register specifies how the framebuffer is con-
figured. Must contain 0xC008007D.
38000188 Refresh Period This read-write register uses the lower 10 bits to specify the
refresh period for the VRAM array.
3800018C Refresh Count The lower 10 bits of this read-only register contains the
number of elapsed cycles between refreshes.
38000190 RAS Low Maximum This read-write register uses the lower 10 bits to specify the
maximum amount of time that the RAS signal can be
asserted. Must contain 0x3FF.
38000194 RAS Low Current The lower 10 bits in this register controls the amount of time
that the RAS signal can be asserted.
Table 11-6 VRAM Control Register Summary
Address Function
38003008 32-bit Absolute value for X[0]
38003010 32-bit Absolute value for Y[0]
38003018 16-bit Absolute value for X[0] and 16-bit Absolute value Y[0]
38003028 32-bit Relative value for X[0]
38003030 32-bit Relative value for Y[0]
38003038 16-bit Relative value for X[0] and 16-bit Absolute value Y[0]
Table 11-7 Device Coordinate Register Addresses
S3GX_TRMBook Page 15 Friday, September 19, 1997 11:39 am