Supermicro SUPERSERVER 2028TP-HC0R-SIOM, Руководство пользователя

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Chapter 7: BIOS
7-9 7-8
SUPERSERVER 2028TP-HTR/HC0R/HC1R-SIOM USER'S MANUAL
X2 APIC (Advanced Programmable Interrupt Controller)
Based on Intel's Hyper-Threading architecture, each logical processor (thread) is
assigned 256 APIC IDs (APIDs) in 8-bit bandwidth. When this feature is set to En-
able, the APIC ID will be expanded (X2) from 8 bits to 16 bits to provide 512 APIDs
to each thread to enhance CPU performance. The options are
Disable and Enable.
AES-NI
Select Enable to use the Intel Advanced Encryption Standard (AES) New Instruc-
tions (NI) to ensure data security. The options are Enable and
Disable .
Intel Virtualization Technology
Select Enable to use Intel Virtualization Technology support for Direct I/O VT-d sup-
port
by reporting the I/O device assignments to the VMM (Virtual Machine Monitor)
through the DMAR ACPI tables. This feature offers fully-protected I/O resource
sharing across Intel platforms, providing greater reliability, security and availability
in networking and data-sharing. The options are
Enable and Disable.

Advanced Power Management Configuration
Advanced Power Management Configuration
Power Technology
Select Energy Efficient to support power-saving mode. Select Custom to custom -
ize system power settings. Select Disabled to disable power-saving settings. The
options are Disable,
Energy Efficient , and Custom.
If the option is set to Energy Efficient or Custom, the following items will display:
Config TDP (Configuring Thermal Design Power)
Select Enable to configure TDP power settings to enhance thermal management.
The options are Enable and Disable .
Config TDP Level (Available when Config TDP above is set to Enable)
Use this item to set TDP configuration level to enhance thermal management.
The options are Nominal , Level 1, and Level 2.

CPU P State Control (Available when Power Technology
is set to Custom)
EIST (P-states)
EIST (Enhanced Intel SpeedStep Technology) allows the system to automatically
adjust processor voltage and core frequency to reduce power consumption and
heat dissipation. The options are Disable and
Enable .
P-state Coordination
This feature is used to change the P-state (Power-Performance State) coordi-
nation type. P-state is also known as "SpeedStep" for Intel processors. Select
HW_ALL to change the P-state coordination type for hardware components only.
Select SW_ALL to change the P-state coordination type for all software installed
in the system. Select SW_ANY to change the P-state coordination type for a soft-
ware program in the system. The options are
HW_All, SW_ALL, and SW_ANY.

CPU C State Control (Available when Power Technology
is set to Custom)
Package C State limit
Use this item to set the limit on the C-State package register. The options are
C0/1 state, C2 state, C6 (non-Retention) state, and
C6 (Retention) state .
CPU C3 Report
Select Enable to allow the BIOS to report the CPU C3 State (ACPI C2) to the
operating system. During the CPU C3 State, the CPU clock generator is turned
off. The options are Enable and
Disable.
CPU C6 Report (Available when Power Technology is set to Custom)
Select Enable to allow the BIOS to report the CPU C6 state (ACPI C3) to the
operating system. During the CPU C6 state, power to all cache is turned off.
The options are
Enable and Disable.
Enhanced Halt State (C1E)
Select Enabled to use Enhanced Halt-State technology, which will significantly
reduce the CPU's power consumption by reducing the CPU's clock cycle and
voltage during a Halt-state. The options are Disable and
Enable .

CPU T State Control (Available when Power Technology
is set to Custom)
ACPI (Advanced Configuration Power Interface) T-States
Select Enable to support CPU throttling by the operating system to reduce power
consumption. The options are
Enable and Disable.