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Sun Microelectronics
17
Cache Organization
3
3.1 Introduction
3.1.1 Level-1 Caches
UltraSPARC’s Level-1 D-Cache is virtually indexed, physically tagged (VIPT).
Virtual addresses are used to index into the D-Cache tag and data arrays while
accessing the D-MMU (that is, the dTLB). The resulting tag is compared against
the translated physical address to determine D-Cache hits.
A side-effect inherent in a virtual-indexed cache is address aliasing; this issue is
addressed in Section 5.2.1, “Address Aliasing Flushing,” on page 28.
UltraSPARC’s Level-1 I-Cache is physically indexed, physically tagged (PIPT).
The lowest 13 bits of instruction addresses are used to index into the I-Cache tag
and data arrays while accessing the I-MMU (that is, the iTLB). The resulting tag
is compared against the translated physical address to determine I-Cache hits.
3.1.1.1 Instruction Cache (I-Cache)
The I-Cache is a 16 Kb pseudo-two-way set-associative cache with 32-byte blocks.
The set is predicted based on the next fetch address; thus, only the index bits of
an address are necessary to address the cache (that is, the lowest 13 bits, which
matches the minimum page size of 8Kb). Instruction fetches bypass the instruc-
tion cache under the following conditions:
•
When the I-Cache enable or I-MMU enable bits in the LSU_Control_Register
are clear (see Section A.6, “LSU_Control_Register,” on page 306)
•
When the processor is in RED_state, or
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