Evaluation board
objectives
UM2027
6/37
DocID029048 Rev 1
Figure 3: Connection of a PFC at the HVDC output
The main STEVAL-IHT008V1 board performance characteristics are:
Efficiency at 230 V 50 Hz 1000 W (only DC resistive load) = 97%
Efficiency at 120 V 60 Hz 500 W (only resistive DC load, rectifier or double modes) =
96%
Standby losses < 150 mW (refer also to section 2.6)
Compliance with IEC 61000-3-3 (with potentiometer "MAX_INRUSH CURRENT" set
to default position; refer to
Section 6: "Inrush-current limitation"
)
Compliance with EN55014 (CIPSPR 22 method B; refer to
Section 10: "EN55014 test
results"
)
IEC 61000-4-4: 2 kV criteria A, T_ICL Triac withstands a 5 kV level without triggering.
This is to avoid undesirable triggering and uncontrolled inrush current due to EMI
noise.
IEC 61000-4-5: 2 kV criteria A
IEC61000-4-11: criteria A for dips down to 100% of the line voltage during 1 cycle;
criteria B for interrupts up to 300 cycles or more (refer to
Section 7: "Mains voltage
dips and interruptions"
).
Figure 4: "Inrush current at STEVAL-IHT008V1 startup on 230 V line (500 µF output DC
capacitor)"
shows an example of the progressive DC capacitor charge ensured by the
T_ICL Triac. The test is performed at startup when the STEVAL-IHT008V1 board is
connected to a 230 V 50 Hz grid, while the output DC capacitor is completely uncharged
(initial voltage is zero). The output DC capacitor is implemented in this case via the series
association of C1 and C9, hence the equivalent capacitance is 500 µF.
The output capacitor is charged in 550 ms with the input RMS current remaining far below
the 16.1 A limit. IEC 61000-3-3 compliance is therefore easily achieved.
