UM2027
Mains
voltage dips and interruptions
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Mains voltage dips and interruptions
IEC 61000-4-11 standard defines the test conditions to evaluate the immunity of equipment
to voltage dips or interruptions. This electromagnetic standard is given as a test method
reference by other standards. For example, product standards like EN55014-2 for
appliances or EN 55024 for IT equipment, which require product compliance in order to be
sold on the European open market, specify the tests to be performed according to IEC
61000-4-11 standard and the expected corresponding tests results.
If a product is not listed in a specific product standard, the general electromagnetic
standard applies according to the use environment (residential or industrial, for example).
As any appliance connected to the mains can be subjected to line voltage dips or
interruptions, a high input current may occur when the line voltage suddenly increases back
to its nominal value to rectifier circuits charging DC capacitors. This high current may
damage the front-end circuit components like the bridge diodes, the AC fuse, etc.
Table 4: "Required dips and interruptions tests and STEVAL-IHT008V1 performance"
gives
the different requirements in terms of line voltage dips and interruptions for the different
electromagnetic immunity standards. In summary, the worst cases to account for are:
Voltage dips: 1 cycle with a 0% residual voltage, and 50 cycles with a 70% residual
voltage
Voltage interruptions: 0% residual voltage during 250 or 300 cycles respectively for 50
and 60 Hz line frequency.
A criteria B is requested for the 0% voltage test during 1 cycle, while the other tests require
only a criteria C.
The MCU firmware of the STEVAL-IHT008V1 board is programmed in order to comply with
these different standard tests with the following strategy:
If the line voltage remains higher than 70% to the reference voltage (measured at
board startup), no change applies to all the Triacs (including T_ICL) orders.
If the line voltage falls below 70% of the reference voltage during at least 1.5 cycles,
all the Triacs (including T_ICL) are switched off. The DC bus voltage will be
discharged by its load current. When the line voltage is reapplied, the T_ICL Triac is
controlled in soft-start again to ensure recharging current limitation. It is clear that
T_ICL restart only occurs if the HVDC ON SPST switch (SW6) is kept to ON position.
the 1.5 cycle duration to detect whether a voltage dip lasts too long is given by
the parameter
Nb_Peak_VAC_Dips
, which is set to 3 by default (meaning 3
times a low peak AC voltage measured). The ratio of voltage decrease from
which value an undervoltage is taken into account is set by the parameter
VAC_Variation_Dips
in the firmware (the default value is 0.3 for 30%
maximum mains voltage reduction).
Table 4: "Required dips and interruptions tests and STEVAL-IHT008V1 performance"
also
provides the test results of the STEVAL-IHT008V1 inrush current limitation function (i.e.,
the T_ICL control). A criteria A is ensured for all dips, even with a 0% residual line voltage,
shorter than 1 cycle. Criteria B is ensured for longer interruptions, even for 300 cycles or
more. The performance of the STEVAL-IHT008V1 board is therefore well above the
performance levels required by international standards.
Figure 16: "(a) Board operation during 1-cycle line interruption"
and
Figure 17: "(b) Board
operation during 2-cycle line interruption"
illustrate board behavior, operating at 230 V with
a 1000 W DC resistive load, for two different voltage dips with a 0% residual voltage
applied during 20 ms (case a) or 40 ms (case b). For case a, the T_ICL Triac is kept ON
