Circuit Description
65
CG635 Synthesized Clock Generator
f
VCO
= RF VCO frequency
f
O
= output frequency
M = DDS clock multiplier (5×)
FTW = 64-bit DDS frequency tuning word
R = reference divider for dual modulus synthesizer. 1
R
16,383
N = VCO divider for dual modulus synthesizer. N = B×P + A with A
B and P=8
D = output divider = 2
n
where 0
n
50
Calculations
Referring to the schematic diagram CG_BLK_C, the output frequency is given by:
f
O
= [ { f
R
× M × FTW / 2
64
} × N / R ] / D
Where the term: { f
R
× M × FTW / 2
64
} = f
DDS
which has the restriction that f
L
f
DDS
f
U
(so that the VCXO can lock to the DDS.)
Given the desired output frequency (f
O
) the procedure to find all of the parameters (D, R,
N and FTW) is:
1.
Use Table 34 to determine the output divider, “D”. If possible, stay within the
current band (i.e., use the current value for D).
2.
Compute the required RF VCO frequency: f
VCO
= f
O
× D.
3.
Find the lowest values for R & N (by enumeration, starting with R=1, and given
that f
VCO
§
f
M
× N / R) so that the desired f
VCO
can be generated consistent the
restriction that f
L
f
VCXO
f
U
(This loop is carried out for f
M
= 19,400,000 Hz
and 19,440,000 Hz. The first iteration to satisfy the loop conditions determines
which VCXO will be selected.)
a.
Start with R=1
b.
Compute the nearest N = INT(0.5 + f
VCO
× R / f
M
)
c.
If N = 46, 47 or 55 (disallowed values) increment R and go to (b.)
d.
Compute the required f
VCXO
= f
VCO
× R / N
e.
Test if the computed f
VCXO
satisfies the condition f
L
f
VCXO
f
U
f.
If the test fails, increment R and go to (b.)
g.
Parse N into A & B registers: B = INT(N/8) & A = N - 8×B
