Specifications
ix
CG635 Synthesized Clock Generator
LVDS Output
(EIA/TIA-644)
Output Rear-panel
RJ-45
Frequency range
DC to 2.05 GHz
Clock output
Pin 1 and pin 2 drive twisted pair
Transition time
<100 ps (20% to 80%)
Source impedance
100
ȍ
between pin 1 and pin 2
Load impedances
100
ȍ
between pin 1 and pin 2
Logic levels
V
LOW
= +0.96 V, V
HIGH
= +1.34 V
Recommended cable
Straight-through Category-6
Protection
Continuous to ground, momentary to +5 V
PRBS (Opt. 01)
(EIA/TIA-644)
Frequency range
DC to 1.55 GHz
Level
LVDS on rear-panel SMA jacks
Outputs
PRBS, –PRBS, CLK & –CLK
PRBS generator
x
7
+ x
6
+ 1 for a length of 2
7
– 1 bits
Transition time
<100 ps (20 % to 80 %)
Load impedance
50
ȍ
to ground on all outputs
Accessory Power
(on rear-panel RJ-45 connector)
+5 VDC
Pin 3
–5 VDC
Pin 5
Ground return
Pin 4 and pin 6
Short circuit protection
Current limited to 375 mA
Polarity clamps
Diode clamps prevent polarity inversion
(2 ADC max., 120 A non-rep.)
General
Computer interfaces
IEEE-488.2 and RS-232 standard. All instrument functions can be
controlled through the computer interfaces.
Non-volatile memory
Ten sets of instrument configurations can be stored and recalled.
Line power
Universal input, 90 to 264 VAC,
47 Hz to 63 Hz
Standby power
<5 W (std. timebase)
<15 W (opt. 02, OCXO timebase)
<25 W (opt. 03, Rb timebase)
Operating power
<30 W (std. timebase)
<40 W (opt. 02, OCXO timebase)
<50 W (opt. 03, Rb timebase)
Dimensions
8.5” × 3.5” × 13” (WHD)
Weight <9
lbs.
Warranty
One year parts and labor on defects in materials and workmanship