CG635 Remote Programming
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CG635 Synthesized Clock Generator
Status Byte Definitions
The CG635 reports on its status by means of the serial poll status byte and four event
status registers: the standard event status (*ESR), the communication error status
(CESR), the PLL lock status (LCKR), and the instrument event status (INSR). These
read-only registers record the occurrence of defined events inside the CG635. If the event
occurs, the corresponding bit is set to one. Bits in the status registers are latched. Once an
event bit is set, subsequent state changes do not clear the bit. Bits are cleared when the
registers are queried, with a *ESR?, for example. The bits are also cleared with the clear
status command, *CLS. The bits are not cleared, however, with an instrument reset
(*RST) or a device clear.
Each of the CG635’s four event status registers has an associated enable register. The
enable registers control the reporting of events in the serial poll status byte (*STB). If a
bit in the event status register is set and its corresponding bit in the enable register is set,
then the summary bit in the serial poll status byte (*STB) will be set. The enable registers
are readable and writable. Reading the enable registers or clearing the status registers
does not clear the enable registers. Bits in the enable registers must be set or cleared
explicitly. To set bits in the enable registers, write an integer value equal to the binary
weighted sum of the bits you wish to set.
The serial poll status byte (*STB) also has an associated enable register called the service
request enable register (*SRE). This register functions in a similar manner to the other
enable registers, except that it controls the setting of the master summary bit (bit 6) of the
serial poll status byte. It also controls whether the CG635 will issue a request for service
on the GPIB bus.
Serial Poll Status Byte
Bit Name Meaning
0
INSB
An unmasked bit in the instrument status register (INSR) has
been set.
1
LCKB
An unmasked bit in the PLL lock status register (LCKR) has
been set.
2
CESB
An unmasked bit in the communications status register (CESR)
has been set.
3 Reserved
4
MAV
The interface output buffer is non-empty.
5
ESB
An unmasked bit in the standard event status register (*ESR)
has been set.
6
MSS
Master summary bit. Indicates that the CG635 is requesting
service because an unmasked bit in this register has been set.
7 Reserved
The serial poll status byte may be queried with the *STB? command. The service request
enable register (*SRE) may be used to control when the CG635 asserts the request-for-
service line on the GPIB bus.
