Circuit Description
89
CG635 Synthesized Clock Generator
The CG641 line receiver converts the LVDS differential clocks to complementary
+3.3 V CMOS outputs on SMA connectors. The CG642 line receiver converts the
LVDS differential clocks to complem2.5 V CMOS outputs on SMA connectors.
The LVDS level clock is received on the 1-2 pair of the RJ-45 connector, J200. The
differential signal is terminated with 100
ȍ
by two resistor networks, N200 and N201.
Undesired common mode signals are terminated by the same networks together with
C207 and C208. The unused RS-485 level clocks on the 7-8 pair are terminated by
R200. The LVDS clocks are converted to complementary 3.3 V CMOS levels by U201
and U202, which are dual LVDS line receivers.
The complementary outputs of U201 and U202 drive the SMA outputs via a resistor
network. The resistor network provides a 50
ȍ
source impedance to reverse terminate
reflected signal. The resistor network also provides attenuation in the CG642, which
provides 2.5 V CMOS output levels.
The outputs are intended to drive any length of un-terminated 50
ȍ
cable. The reflection
from the unterminated end is reverse terminated by the output’s 50
ȍ
impedance.
Terminating the outputs will not damage the module, but doing so will reduce the
amplitude of the outputs by a factor of 2×.
CG643-CG645 line receivers
Schematic sheet “CG_LR3B”
The CG643-CG645 line receivers convert differential LVDS clocks to complementary
PECL outputs on SMA connectors. These three line receivers use the same PCB and
circuit design. The voltage source for the logic “1” level (U300) is set for a particular
output logic level, as is the magnitude of the switched current which controls the
amplitude of the logic transition.
The LVDS level clock is received on the 1-2 pair of the RJ-45 connector, J300. The
differential signal is (primarily) terminated by R302 and R303. Undesired common
mode signals are terminated by R304 and C323. The unused RS-485 level clocks are
terminated by R300.
The LVDS clock input is AC coupled to an ECL line receiver, U303. The clocks’ DC
levels are summed with the AC levels by the (slow) differential amplifiers U302A and
U302B. The output of the line receiver is passed to a laser diode driver, U304 a
MAX3737, which provides fast (
§
60 ps), switched, differential, programmable current
sources to drive the SMA outputs.
The MAX3737 has other features which are not used here but which need to be
accommodated so as to avoid apparent “fault” conditions. The transistor Q300 imitates a
laser diode’s photo monitor by providing small current that increases with the
MAX3737’s bias current generator. U305 provides a reset to U304 in the case that a
fault should occur. The magnitude of the current switched by U304 is controlled by
R308.
Both SMA outputs should be terminated with 50
ȍ
loads. (Except for the CG643, which
pr5 V PECL level outputs into unterminated 50
ȍ
cables.)
