Circuit Description
64
CG635 Synthesized Clock Generator
Programmable Dividers and Clock Fan-out
A high speed (>2 GHz) digital divider is used to scale the 960-2050 MHz clock to lower
frequencies. There are fifty-one, overlapping octave bands to span the frequency range
between 1 µHz and 2.05 GHz. If a new output frequency is specified, the firmware will
attempt to stay within the same octave band. If an octave switch is required, however,
and the frequency is in one of the first eleven octave bands, the output will go to a low
state until the VCO has settled, and then the output will be re-enabled in a “runtless”
fashion.
Table 34: CG635’s Fifty-one, Overlapping Octave Bands
Band
Divider
Min Frequency (Hz)
Max Frequency (Hz)
0 1 960,000,000 2,050,000,000
1 2 480,000,000 1,024,000,000
2 4 240,000,000
512,000,000
3 8 120,000,000
256,000,000
4 16 60,000,000
128,000,000
5 32 30,000,000
64,000,000
6 64 15,000,000
32,000,000
7 128
7,500,000
16,000,000
8 256
3,750,000
8,000,000
9 512
1,875,000
4,000,000
10 1024
937,500
2,000,000
11 2048
468,750
1,000,000
…
…
…
…
49 2
49
0.000,001,705,302 0.000,003,637,978
50 2
50
0.000,000,852,651 0.000,001,818,989
For frequencies in bands eleven to fifty, the CG635 uses DDS technology to seamlessly
change dividers. Since no spurious pulses are generated, the output is not disabled.
Determining Register Values
Definitions
f
R
= 20 MHz timebase reference (which can be locked to an external 10 MHz)
f
DDS
= DDS synthesizer output frequency (±100 ppm of 19.40 MHz or 19.44 MHz)
f
VCXO
= VCXO frequency (±100 ppm of 19.40 MHz or 19.44 MHz)
f
U
= upper tuning limit of f
VCXO
(100 ppm above f
M
)
f
M
= nominal f
VCXO
frequency (19,400,000 Hz or 19,440,000 Hz)
f
L
= lower tuning limit of f
VCXO
(100 ppm below f
M
)
f
C
= phase detector comparison frequency
