Circuit Description
73
CG635 Synthesized Clock Generator
cause the integrating loop filter to ramp upward, increasing voltage on the varactor
(D200 or D201) and so increase the frequency of the VCXO until it is brought in-phase
with the DDS.
Minimum pulse widths will be seen at the Q outputs of U207A/B when the PLL circuit
achieves phase-lock. The pulse widths will be equal to the sum of the propagation delays
through the OR gate (U208, 0.9-3.6 ns) and the flip-flops (U207, 1.0-5.4 ns). For
propagation delay sums between 1.9 ns and 9 ns, and a period of 51.5 ns, the duty cycle
of the 3.3 V pulse is between 3.6 % and 17 % leading to a voltage of 118 mV to 561 mV
on the pre-filter outputs (19MHZ_LEAD and 19MHZ_LAG.) Hence the criteria for
phase lock of the VCXO to the DDS are that 19MHZ_LEAD and 19MHZ_LAG be
between 100 mV and 600 mV and within 20 mV of each other. The PLL bandwidth is
20 Hz.
The varactor voltage can operate between 0 and +15 VDC to tune the VCXO over a
range of about ±180 ppm. The frequency synthesizer design only requires a range of
±100 ppm; hence, the varactor voltage will not need to go to the rails. An attenuated and
filtered version of the varactor voltage (19 MHZ_VC) may be read via the
microcontroller’s ADC to verify the tuning range of the VCXO.
Time Modulation
Main Board, Schematic sheet “CG_MB3D”
The CG635 has a rear panel time-modulation input (J300) which allows an analog
voltage to modulate the timing of the clock outputs. This input is calibrated to have a
sensitivity of 1 ns/V and a full-scale range of ±5 ns. The input is DC coupled and so may
be used as a DC phase adjustment of the clock outputs. Broadband noise applied to this
input will cause broadband output jitter (within the bandwidth of the RF PLL).
The selected 19 MHz VCXO is used as a frequency reference to the dual-modulus RF
PLL synthesizer. Since the synthesizer phase locks its RF output to the reference input,
time-modulation of the reference will time-modulate the clock outputs. The frequency
reference is time modulated by converting the 19 MHz square wave from the output of
U213 to a linear ramp on C302, applying the linear ramp and the time-modulation signal
to the inputs of a fast comparator (U302), and using the output of the comparator as the
frequency reference for the RF synthesizer (U307).
The linear ramp on C302 is created by equal opposing current sources which are
alternately applied to C301 or C302 by the diode bridge (D300/D301). When the
19 MHz output from U301 is low, the current sourced by U300A via L300 and R304 is
shunted to C301, causing C302 to ramp down. When the 19 MHz output from U301 is
high, the current drawn by U300B via L301 and R305 is sourced by C301, causing C302
to ramp up. The positive current source (U300A) is controlled by the analog signal
CAL_TMOD so as to calibrate the rear panel time-modulation input sensitivity. The
negative current source (U300B) is configured to maintain the ramp on C302 so that it is
symmetrical about ground.
The time modulation input (J300) is filtered, attenuated and limited by R308-312, C307,
C308, and D302 before being applied to the comparator (U302). The input impedance of
