Hardware layout and configuration
UM1668
12/70
DocID025151 Rev 2
The LED LD10 is lit when the STM32439I-EVAL evaluation board is powered by the 5 V
correctly.
Note:
In order to avoid the impact of USB PHY and Ethernet PHY and get precise results of
current consumption on JP2, the following configurations must be implemented:
•
Configure Ethernet PHY in Power Down Mode by setting low level of IO_Expander
(EXP_IO1).
•
Configure USB HS PHY in Low Power Mode (Register Address=04,bit 6 in USB PHY).
JP12 (continued)
For power supply from USB OTG2 FS (CN15) to
STM32439I-
EVAL
only, JP12 is set as shown to the right:
For power supply from USB OTG1 FS (CN14) to
STM32439I-
EVAL
only, JP12 is set as shown to the right:
For power supply from USB OTG2 HS (CN9) to
STM32439I-
EVAL
only, JP12 is set as shown to the right:
For power supply from power supply jack(CN18) to both
STM32439I-EVAL
and daughterboard connected on CN6 &
CN7, JP12 is set as shown to the right (daughterboard must not
have its own power supply connected)
Table 2. Power related jumpers (continued)
Jumper
Description
+6
)6
)6
'9
368
67ON
+6
)6
)6
'9
368
67ON
+6
)6
)6
'9
368
67ON
+6
)6
)6
'9
368
67ON
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