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Electrical characteristics
ST7LITEUS2, ST7LITEUS5
114/136
Refer also to
Section 11.2.1: Illegal opcode reset
for more details on illegal opcode reset
conditions.
Figure 61.
RESET pin
protection when LVD is enabled
1.
When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-
down capacitor is required to filter noise on the reset line.
2.
When using the LVD:
- Check that all recommendations related to ICCCLK and reset circuit have been applied (see caution in
and text above)
- Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709
and AN2017. If this cannot be done, it is recommended to put a 100nF + 1M
Ω
pull-down on the RESET
pin.
- The capacitors connected on the RESET pin and also the power supply are key to avoid any startup
marginality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace
10nF pull-down on the RESET pin with a 5µF to 20µF capacitor.”
3.
In case a capacitive power supply is used, it is recommended to connect a 1M
Ω
pull-down resistor to the
RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will
add 5µA to the power consumption of the MCU).
Table 65.
Asynchronous RESET pin characteristics
(1)
1.
T
A
= -40°C to 125°C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
IL
Input low level voltage
V
SS
-
0.3
0.3V
DD
V
V
IH
Input high level voltage
0.7V
DD
V
DD
+
0.3
V
hys
Schmitt trigger voltage
hysteresis
(2)
2.
Data based on characterization results, not tested in production.
2
V
V
OL
Output low level voltage
(3)
3.
The I
IO
current sunk must always respect the absolute maximum rating specified in
of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
V
DD
=5 V I
IO
=+2 mA
400
mV
R
ON
Pull-up equivalent resistor
(4)
4.
The R
ON
pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin
between V
ILmax
and V
DD.
V
IN
=
V
SS
V
DD
=5 V
30
50
70
k
Ω
V
DD
=3 V
90
t
w(RSTL)out
Generated reset pulse duration
Internal reset sources
90
μ
s
t
h(RSTL)in
External reset pulse hold time
(5)
5.
To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses
applied on RESET pin with a duration below t
h(RSTL)in
can be ignored.
20
μ
s
t
g(RSTL)in
Filtered glitch duration
200
ns
0.01
μ
F
ST7XXX
PULSE
GENERATOR
Filter
R
ON
V
DD
INTERNAL
RESET
RESET
EXTERNAL
Required
1M
Ω
Optional
(note 3)
WATCHDOG
LVD RESET
ILLEGAL OPCODE
5)
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