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ST7LITEUS2, ST7LITEUS5
Electrical characteristics
113/136
Figure 59.
Typical V
OL
vs. V
DD
(HS pins)
Figure 60.
Typical V
DD
-V
OH
vs. V
DD
(HS pins)
12.9
Control pin characteristics
The reset network protects the device against parasitic resets.
The output of the external reset circuit must have an open-drain output to drive the ST7
reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset
(LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level on the
RESET pin can go below the V
IL
max. level specified in
. Otherwise the reset will
not be taken into account internally.
Because the reset circuit is designed to allow the internal reset to be output in the RESET
pin, the user must ensure that the current sunk on the RESET pin is less than the absolute
maximum value specified for I
INJ(RESET)
Refer to
and
for a description of the RESET pin protection circuit with
LVD enabled and disabled.
40
50
60
70
80
90
100
2.4
2.6 2.8
3
3.2
3.4 3.6
3.8
4
4.2 4.4
4.6
4.8
5
5.2
5.4
5.6 5.8
6
Vdd [V]
VO
L
[
m
V]
v
s
VD
D
a
t
IL
O
A
D
=
2
m
A
-45°C
25°C
90°C
130°C
100
150
200
250
300
350
400
450
500
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
4
4.2
4.4
4.6
4.8
5
5.2
5.4
5.6
5.8
6
Vdd [V]
VO
L
[
m
V]
v
s
VD
D
a
t I
L
O
A
D
=
8
m
A
-45°C
25°C
90°C
130°C
200
300
400
500
600
700
800
900
2.4
2.6 2.8
3
3.2
3.4
3.6 3.8
4
4.2
4.4
4.6 4.8
5
5.2
5.4
5.6 5.8
6
Vdd [V]
V
O
L [mV
]
v
s
V
D
D
at
I
L
O
A
D
=
12m
A
-45°C
25°C
90°C
130°C
40
60
80
100
120
140
160
180
200
2.4 2.6
2.8
3
3.2 3.4
3.6 3.8
4
4.2 4.4
4.6 4.8
5
5.2
5.4 5.6
5.8
6
Vdd [V]
VD
D
-VO
H
[
m
V]
v
s
VD
D
@
I
L
O
A
D
=
2
m
A
-45°C
25°C
90°C
130°C
100
200
300
400
500
600
700
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
4
4.2
4.4
4.6
4.8
5
5.2
5.4
5.6
5.8
6
Vdd [V]
V
DD-
V
O
H [
m
V
]
v
s
V
DD @
I
L
O
A
D=
6
m
A
-45°C
25°C
90°C
130°C
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