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UM0404 Multiply-accumulate unit (MAC)
In this example, the BFLDL instruction performs a read access to the MSW during the
decode stage while the MSW.Z flag is only set at the end of the execute stage of the
CoADD.
4.2.3 Address generation
MAC instructions can use some standard ST10 addressing modes such as GPR direct or
#data4 for immediate shift value.
New addressing modes have been added to supply the MAC with two new operands per
instruction cycle. These allow indirect addressing with address pointer post-modification.
Double indirect addressing requires two pointers. Any GPR can be used for one pointer, the
other pointer is provided by one of two specific SFRs IDX0 and IDX1. Two pairs of offset
registers QR0/QR1 and QX0/QX1 are associated with each pointer (GPR or IDX
i
). The GPR
pointer allows access to the entire memory space, but IDX
i
are limited to the internal IRAM,
except for the CoMOV instruction.
The following table shows the various combinations of pointer post-modification for each of
these two new addressing modes. In this document the symbols “[Rw
n
⊗
]” and “[IDX
i
⊗
]”
refer to these addressing modes.
For the CoMACM class of instruction, Parallel Data Move mechanism is implemented. This
class of instruction is only available with double indirect addressing mode. Parallel Data
Move allows the operand pointed by IDX
i
to be moved to a new location in parallel with the
MAC operation. The write-back address of Parallel Data Move is calculated depending on
Code MSW (before) MSW (after) Comment
MOV MSW, #0 - 0000h
MOV R0, #0 - -
CoADD R0, R0 0000h 0200h MSW.Z set at execute
BFLDL MSW, #FFh, #FFh 0200h 00FFh Error!
Table 10. Pointer post-modification combinations for IDXi and Rwn
Symbol Mnemonic Address pointer operation
“[IDX
i
⊗
]” stands for
[IDX
i
] (IDX
i
)
←
(IDX
i
) (no-op)
[IDX
i
+
] (IDX
i
)
←
(IDX
i
) +2 (i = 0,1)
[IDX
i
-] (IDX
i
)
←
(IDX
i
) -2 (i = 0,1)
[IDX
i
+
QX
j
] (IDX
i
)
←
(IDX
i
) + (QX
j
) (i, j = 0,1)
[IDX
i
- QX
j
] (IDX
i
)
←
(IDX
i
) - (QX
j
) (i, j = 0,1)
“[Rw
n
⊗
]” stands for
[Rw
n
] (Rw
n
)
←
(Rw
n
) (no-op)
[Rw
n
+
] (Rw
n
)
←
(Rw
n
) +2 (n = 0-15)
[Rw
n
-] (Rw
n
)
←
(Rw
n
) -2 (k = 0-15)
[Rw
n
+
QR
j
] (Rw
n
)
←
(Rw
n
) + (QR
j
) (n = 0-15; j = 0,1)
[Rw
n
- QR
j
] (Rw
n
)
←
(Rw
n
) - (QR
j
) (n = 0-15; j = 0,1)