The central processing unit (CPU)
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The central processing unit (CPU)
The CPU is used to fetch and decode instructions, to supply operands for the arithmetic and
logic unit (ALU), to perform operations on these operands in the ALU, and to store the
previously calculated results.
A four stage pipeline is implemented, where up to four instructions can be processed in
parallel. Most instructions of the ST10F276 are executed in one instruction cycle due to this
parallelism.
This section describes how the pipeline works for sequential and branch instructions in
general, and which hardware provisions have been made to speed the execution of jump
instructions in particular. The general instruction timing is described, including standard and
exceptional timing.
While internal memory accesses are normally performed by the CPU itself, external
peripheral or memory accesses are performed by a particular on-chip External Bus
Controller (EBC), which is automatically invoked by the CPU whenever a code or data
address refers to the external address space.
If possible, the CPU continues to operate while an external memory access is in progress. If
external data are required but are not yet available, or if a new external memory access is
requested by the CPU, before a previous access has been completed, the CPU will be held
by the EBC until the request can be satisfied. The EBC is described in
external bus interface on page 181
.
The on-chip peripheral units of the ST10F276 are almost independent of the CPU, with a
separate clock generator. Data and control information is interchanged between the CPU
and these peripherals via Special Function Registers (SFRs).
Whenever peripherals need a non-deterministic CPU action, an on-chip Interrupt Controller
compares all pending peripheral interrupt requests and prioritizes one of them.
If the priority of the current CPU operation is lower than the priority of the selected peripheral
request, an interrupt service will occur. There are two types of interrupt processing:
1.
Standard interrupt processing
forces the CPU to save the current program status
and return address on the stack before branching to the interrupt vector jump table.
2.
PEC interrupt processing
steals just one instruction cycle from the current CPU
activity to perform a single data transfer via the on-chip PEC.
System errors detected during program execution (so called hardware traps), or an external
non-maskable interrupt, are also processed as high priority standard interrupts.
There is a close conjunction between the watchdog timer and the CPU. If enabled, the
watchdog timer expects to be serviced by the CPU within a programmable period of time,
otherwise it will reset the chip.
Therefore, the watchdog timer is able to prevent the CPU from erratic behaviour when
executing erroneous code. After reset, the watchdog timer starts counting automatically, but
if necessary it can be disabled via software.