Sony MEX-1HD - Audio Library System, Руководство по обслуживанию

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79
MEX-1HD
Pin No. Pin Name I/O Description
123 ID_IORDY I ATAPI bus ready signal input from the LC895300 and HDD
124 ID_XDIOR O ATAPI bus IOR signal output to the LC895300 and HDD
125 ID_XDIOW O ATAPI bus IOW signal output to the LC895300 and HDD
126 VCC — Power supply terminal (+5V)
127, 128
ID1_XCS0,
ID1_XCS1
O
ATAPI bus chip select signal output to the LC895300
129, 130 VSS — Ground terminal
131, 132 T, W
I
For test terminal (normally: fixed at “L”)
133 VDD — Power supply terminal (+3.3V)
134 CU_RXCLK
I
Cuckoo I/F RX data receive clock signal input terminal Not used
135 CU_RXDAT
I
Cuckoo I/F RX data input terminal Not used
136 CU_STRDI
I
Cuckoo I/F strobe/ready signal input terminal Not used
137 CU_CONH
I
Cuckoo I/F monitor signal input terminal Not used
138 CU_STRD0
O
Cuckoo I/F strobe/ready signal output terminal Not used
139 CU_TXDAT
O
Cuckoo I/F TX data output terminal Not used
140 CU_TXCLK
O
Cuckoo I/F TX data transfer clock signal output terminal Not used
141 VSS — Ground terminal
142 CU_TXOSC
O
Cuckoo I/F TX data transfer clock source output terminal Not used
143 VDD — Power supply terminal (+3.3V)
144, 145
EX_XWAIT1,
EX_XWAIT0
I Wait signal input terminal Not used
146 EX_XIRQ0 I Interrupt request signal input from the memory stick interface IC
147 EX_XIRQ1 I Interrupt request signal input from the USB interface IC
148 to
151
SH_XIRL0 to
SH_XIRL3
O
Interrupt request signal output to the CPU
152 SH_XWAIT
O
Wait signal output to the CPU
153 SH_XRST I System reset signal input from the system controller
154 SH_XRD
I
Read strobe signal input to the CPU
155 SH_XRDWR
I
Read/write signal input from the CPU
156 157
XWE0,
SH_XWE1
I
Write enable signal input from the CPU
158 SH_XBS
I
Bus start signal input from the CPU
159 VSS — Ground terminal
160 SH_CKIO I System clock signal input from the CPU
161 VDD — Power supply terminal (+3.3V)
162 SH_XCS
I
Chip select signal input from the CPU
163 to
165
SH_A25 to
SH_A23
I
Address signal input from the CPU
166 to
179
SH_A20 to
SH_A07
I Address signal input from the CPU
180 VSS — Ground terminal
181, 182 SH_A06, SHA05 I Address signal input from the CPU
183 VDD — Power supply terminal (+3.3V)
184 to
187
SH_A04 to
SH_A01
I Address signal input from the CPU