Sony MEX-1HD - Audio Library System, Руководство по обслуживанию

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83
MEX-1HD
Pin No. Pin Name I/O Description
56, 57 HD9, HD6 I/O Two-way AV data bus with the CPU/ATA interface IC
58 CVDD — Power supply terminal (+1.8V)
59, 60 HD4, HD3 I/O Two-way AV data bus with the CPU/ATA interface IC
61 DVDD — Power supply terminal (+3.3V)
62 EXT_INT6 I AV bus block data transfer completely signal input from the CPU/ATA interface IC
63 RSV3 O Reserved terminal Not used
64 VSS — Ground terminal
65, 66 CVDD — Power supply terminal (+1.8V)
67 CLKOUT1 O Clock signal output terminal Not used
68 VSS — Ground terminal
69, 70 EMU0, EMU2 I/O Emulation terminal Not used
71 CVDD — Power supply terminal (+1.8V)
72 RSV1 O Reserved terminal Not used
73 VSS — Ground terminal
74, 75 CVDD — Power supply terminal (+1.8V)
76 DVDD — Power supply terminal (+3.3V)
77 VSS — Ground terminal
78 HD2
I/O
Two-way AV data bus with the CPU/ATA interface IC
79 DVDD — Power supply terminal (+3.3V)
80 HD1
I/O
Two-way AV data bus with the CPU/ATA interface IC
81 CLKS1 I Clock source signal input terminal Not used
82 VSS — Ground terminal
83 EXT_INT7 I AV bus block data transfer completely signal input from the CPU/ATA interface IC
84, 85 VSS — Ground terminal
86 XHAS I Host address strobe signal input terminal Not used
87 XHDS1 I AV bus data strobe signal input from the XC9536XL
88 HD0
I/O
Two-way AV data bus with the CPU/ATA interface IC
89
TOUT1
(AV_DRQ2)
O
AV bus data request signal output to the CPU/ATA interface IC
90 TINP1 I Timer or general-purpose input terminal Not used
91 DVDD — Power supply terminal (+3.3V)
92, 93 CVDD — Power supply terminal (+1.8V)
94 XHDS2 I Host data strobe signal input terminal Not used
95 VSS — Ground terminal
96 XHCS
I
AV bus chip select signal input from the XC9536XL
97
TOUT0
(AV_DRQ1)
O
AV bus data request signal output to the CPU/ATA interface IC
98 TINP0 I Timer or general-purpose input terminal Not used
99 CLKX0
O
Clock signal output terminal Not used
100, 101 VSS — Ground terminal
102, 103
HCNTL0,
HCNTL1
I
AV bus address signal input from the CPU/ATA interface IC
104 HR/XW
I
AV bus read or write enable signal input from the CPU/ATA interface IC
105 FSX0 O Frame sync signal output terminal Not used
106 DX0 O Data signal output terminal Not used
107 CLKR0
I
Clock signal input terminal Not used
108, 109 VSS — Ground terminal