Sony MEX-1HD - Audio Library System, Руководство по обслуживанию

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69
MEX-1HD
6-33. IC PIN FUNCTION DESCRIPTION
•
SERVO BOARD IC8 LC895300 (ATAPI, DSP, CD-ROM DECODER)
Pin No. Pin Name I/O Description
1 VSS — Ground terminal
2 to 4 A11, A9, A8 O Address signal output to the flash memory
5, 6 A13, A14 O Address signal output to the flash memory
7 WSTROBE O Write strobe signal output to the flash memory
8 to 10 A16, A15, A12 O Address signal output to the flash memory
11 to18 A7 to A0 O Address signal output to the flash memory
19, 20
DATA0, DATA1
I/O Two-way data bus with the flash memory
21 VDDD — Power supply terminal (+5V)
22 VDD1 — Power supply terminal (+3.3V)
23 VSS — Ground terminal
24 VSSD — Ground terminal
25 to 30
DATA2 to DATA7
I/O Two-way data bus with the flash memory
31 ZCE O Chip enable signal output to the flash memory
32 A10 O Address signal output to the flash memory
33 PSEN O Ready signal output to the flash memory
34 IOPORT0 I/O Not used
35 IOPORT1 I Tray close-end signal input
36 IOPORT2 I/O Not used
37 TEST0 I For test terminal (normally: fixed at “L”)
38
WRQ/HFLO/DIR
/TLOCK
O
Monitor output terminal Not used
39 FSEQ/DEF
O
Frame detection signal output or defect signal output terminal Not used
40 DOUT/TESO
O
Digital audio signal output or TES signal output terminal Not used
41 VDD0 — Power supply terminal (+5V)
42 VSS — Ground terminal
43 PLL1
O
PLL clock signal output terminal Not used
44 PLL1VDD — Power supply terminal (+3.3V)
45 PLL1VSS — Ground terminal
46 CSEL
I
Not used
47 ZHRST
I
Not used
48 ZDASP
I/O
Not used
49, 50
ZCS3FX,
ZCS1FX
I
ATAPI bus chip select signal input from the CPU/ATA interface IC
51 VSS1 — Ground terminal
52 VDD0 — Power supply terminal (+5V)
53, 54 DA2, DA0
I
ATAPI bus address signal input from the CPU/ATA interface IC
55 ZPDIAG
I/O
Not used
56 DA1
I
ATAPI bus address signal input from the CPU/ATA interface IC
57 ZIOCS16
O
Chip select signal output terminal Not used
58 VSS1 — Ground terminal
59 HINTRQ
O
Interrupt request signal output to the CPU/ATA interface IC
60 ZDMACK
I
ATAPI bus DMA acknowledge signal input from the CPU/ATA interface IC
61 IORDY
O
ATAPI bus ready signal output to the CPU/ATA interface IC
62 ZDIOR
I
ATAPI bus IOR signal input from the CPU/ATA interface IC
63 ZDIOW
I
ATAPI bus IOW signal input from the CPU/ATA interface IC
64 DMARQ
O
ATAPI bus DMA request signal output to the CPU/ATA interface IC