SH61F83
44
CRSEQ STLCR STLCW
Valid OUT0 Data 0
Valid OUT0 Data 1
Valid IN0 Token
Note
0
0
0
STLT0 = 0 & STLR0 = xx
STLT0 = 0 & STLR0 = xx
STLT0 = xx & STLR0 = 0
1
0
0
STLT0 = 0 & STLR0 = xx
STLT0 = 0 & STLR0 = xx
STLT0 = xx & STLR0 = 0
0
1
0
STLT0 = 1 & STLR0 = 1
STLT0 = 1 & STLR0 = 1
STLT0 = xx & STLR0 = 0
1
1
0
STLT0 = 0 & STLR0 = xx
STLT0 = 1 & STLR0 = 1
STLT0 = xx & STLR0 = 0
0
0
1
STLT0 = 0 & STLR0 = xx
STLT0 = 0 & STLR0 = xx
STLT0 = 1 & STLR0 = 1
1
0
1
STLT0 = 0 & TLR0 = xx
STLT0 = 0 & STLR0 = xx
STLT0 = 1 & STLR0 = 1
0
1
1
STLT0 = 0 & STLR0 = 1
STLT0 = 0 & STLR0 = 1
STLT0 = 1 & STLR0 = 0
Illegal
1
1
1
STLT0 = 0 & STLR0 = xx
STLT0 = 0 & STLR0 = 1
STLT0 = 1 & STLR0 = 0
Illegal
Note1: xx means unchanged
Note2: Set the control register in the illegal condition will result in abnormal state under EP0 Control Read/Write Transfer.
The RX FIFO operational model refers to Figure 10-2.
In the following, the related F/W procedures and H/W actions are described.
(1) After Hardware Reset or USB Reset, the R0FULL bit in RXFLG0 will reset to 0 to announce no data in RXDAT0 FIFO.
(2) SIE receives data (a valid SETUP Transaction or a valid OUT Transaction) byte-by-byte from USB transceiver.
(3) SIE issues ACK.
(4) A SETUP or OUT IRQ occurs and H/W writes data and bytes count to the RXDAT0 and RXCNT0 registers.
(5) H/W sets the R0FULL bit to “1”.
(6) After F/W read data from RXDAT0 FIFO, F/W has to set the R0FULL bit to “0”.
Hardware Reset or
USB Reset
set RXDAT0 = NULL
Firmware Process
Read RXDAT0 FIFO
set R0FULL = 0
A valid SETUP or
OUT transaction IRQ ?
NO
set RXDAT0 = RX data
set RXCNT = bytes count
set R0FULL = 1
YES
Hardware
Firmware
set R0FULL = 0
Figure 10-2. RXFIFO Operation Model
