Sino Wealth SH61F83, Руководство пользователя

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SH61F83
17
5.2. Watch-dog Timer Reset
The SH61F83 implements a Watchdog timer to avoid system stop or malfunction. The clock source of the WDT is F
SYS
. The
time-out interval of Watchdog timer is selected by PREWDT[1:0] . The Watchdog timer must be cleared within time-out period;
otherwise the Watchdog timer will overflow and cause a system reset. The Watchdog timer is cleared and enabled after the
system is reset, and can be disabled by the software only on idle mode. Users can clear the Watchdog timer by writing a #55H
to the
CLRWDT (0093H) register.
0093H CLRWDT Initial Value Clear Watch-dog Timer Control Register
Bit[7:0]
CLRWDT
[7:0]
55H W
Write “55H” to clear watch-dog timer
Reset source: Hardware reset, USB reset, WDT reset, Resume reset
0094H PREWDT Initial Value Watch-dog Timer Pre-scalar Control Register
Bit[7:2] - 000000b - Reserved
Bit[1:0]
PREWDT
[1:0]
00b R/W
Watch-dog timer Pre-scalar control register
00: 2
16
T
SYS
(10.922ms)
01: 2
17
T
SYS
(21.845ms)
10: 2
18
T
SYS
(43.688ms)
11: 2
19
T
SYS
(87.376ms)
Reset source: Hardware reset, USB reset, WDT reset, Resume reset
Note1: The new Pre-scalar value will be loaded after the Watchdog Timer was cleared (write #55H to CLRWDT register)
Note2: When system enters Power-Down Mode, WDT will stop due to the lack of T
SYS
. When system resumes from
Power-Down Mode, the WDT control register will be cleared to the initial state.
5.3. IDLE and Power-Down Mode
The SH61F83 has two power-reducing modes:

IDLE mode ( IDL = 1 & SUSLO = 55H): The CPU is frozen, but otherwise the circuit continues to run.

Power-down mode ( PD = 1 & SUSLO = 55H): The oscillator is frozen.
008EH SUSLO Initial Value Power saving Control Register 1
Bit[7:0]
SUSLO
[7:0]
00H R/W
IDL = 1 & SUSLO = 55H: Enter idle mode
PD = 1 & SUSLO = 55H: Enter Power-down mode
Reset source: Hardware reset, USB reset, WDT reset, Resume reset
0087H PCON Initial Value Power saving Control Register 2
Bit[7:2] - 000000b - Reserved
Bit1 PD 0b R/W
PD = 1 & SUSLO = 55H: Enter Power-down mode
Reset source: Hardware reset, USB reset, WDT reset, Resume reset
Bit0 IDL 0b R/W
IDL = 1 & SUSLO = 55H: Enter idle mode
Reset source: Hardware reset, USB reset, WDT reset, Resume reset
6MHz
RC
resonator
PD
IDL
MCU
to Interrupt,
Port, Timer,
Watch-dog Timer
F
SYS
CLOCK
GEN
to USB SIE
IDLE
CONTROL
CIRCUIT
Figure 5-6. Sketch map for IDLE and Power-Down Mode implement