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Sino Wealth SH61F83, Руководство пользователя

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SH61F83

 

41 

 

00E4H 

TXFLG1 

Initial Value 

USB TX FIFO 1 Flag/Control Register 

Bit[7:4] 

- 

0000B 

- 

Reserved 

Bit3 

T1EPE 

0b 

R/W 

This bit is used to enable/disable the endpoint 1 

1: Enable endpoint 1 
0: Disable, the corresponding endpoint does not respond to a valid IN Token 

Reset source: Hardware reset or USB reset 

Bit2 

T1SEQC 

0b 

W 

The data sequence of each transmitted data packet is controlled by hardware 
and is toggled after receiving ACK from host. The F/W can reset the data 
sequence by writing “1” to T1SEQC for resetting the next transmitting data 
sequence on endpoint 1. Write “0” to no effect. 
Read this bit will always get value with “0” 

Reset source: Hardware reset or USB reset 

Bit1 

STLT1 

0b 

R/W 

Pipe 1 stall bit

, this bit is used to stall the pipe 1. STL1 is set by SETUP 

command - SetFeature (ENDPOINT_HALT) and STL1 is reset by SETUP 
command - ClearFeature (ENDPOINT_HALT). 
0: responds ACK, NAK or not respond to IN1 
1: STLT1 bit is used to stall the pipe 1 IN token. SIE will respond STALL to 
Host IN token as long as STLT1 bit is set 

Reset source: Hardware reset or USB reset 

Bit0 

T1FULL 

0b 

R/W 

TXDAT1 FIFO full status bit

. F/W writes “1” to set H/W FIFO pointer. 

Clear to “0” by H/W after receiving ACK form host. 
0: Empty 
1: Full 

Reset Source: Hardware reset, USB reset   

 

00E7H 

TXFLG2 

Initial Value 

USB TX FIFO 2 Flag/Control Register 

Bit[7:4] 

- 

0000B 

- 

Reserved 

Bit3 

T2EPE 

0b 

R/W 

This bit is used to enable the endpoint 2

. 

1: Enable endpoint 2 
0: Disable, the corresponding endpoint does not respond to a valid IN Token 

Reset source: Hardware reset or USB reset 

Bit2 

T2SEQC 

0b 

W 

The data sequence of each transmitted data packet is controlled by hardware 
and is toggled after receiving ACK from host. The F/W can  reset the data 
sequence by writing “1” to T2SEQC for resetting the next transmitting data 
sequence on endpoint 2. Write “0” to no effect. 
Read this bit will always get value with “0” 

Reset source: Hardware reset or USB reset 

Bit1 

STLT2 

0b 

R/W 

Pipe 2 stall bit

, this bit is used to stall the pipe 2. STL2 is set by SETUP 

command  -  SetFeature  (ENDPOINT_HALT) and STL2 is reset by SETUP 
command - ClearFeature (ENDPOINT_HALT).   
0: responds ACK, NAK or not respond to IN2 
1: STLT2 bit is used to stall the pipe 2 IN token. SIE will respond STALL to 
Host IN token as long as STLT2 bit is set 

Reset source: Hardware reset or USB reset 

Bit0 

T2FULL 

0b 

R/W 

TXDAT 2 FIFO full status bit

. F/W writes “1” to set H/W FIFO pointer. 

Clear to “0” by H/W after receiving ACK form host. 
0: Empty 
1: Full 

Reset Source: Hardware reset or USB reset 

 

Содержание SH61F83

Страница 1: ...ddress with 3 endpoints endpoint 0 1 and 2 Built in 1 5Kohms USB pull up resistor Built in Watch Dog Timer WDT Two blue LED port Reset Hardware reset External reset Power on reset Low voltage reset US...

Страница 2: ...P04 17 P05 18 P06 19 P07 20 P10 21 P11 22 P12 23 P13 24 P14 1 P46 VDM EXT0 2 P30 3 P31 4 P32 5 P33 6 P34 7 P35 8 P36 BLED0 9 P37 BLED1 10 RSTB 11 P00 12 P01 SH61F83Q SH61F83 48 Pin QFN Package Pad Con...

Страница 3: ...6 EXT0 P00 P07 P10 P17 P20 P27 P30 P37 GND RSTB 6MHz OSC Power On Reset USB Transceiver I O PORTs P40 P42 LED 0 2 Wake up Timer VDD 3 3V REGULATOR Power Down Mode Controller Low Voltage Reset 32KHz OS...

Страница 4: ...07 I O Bi directional I O pin 20 21 P10 I O Bi directional I O pin 21 22 P11 I O Bi directional I O pin 22 23 P12 I O Bi directional I O pin 23 24 P13 I O Bi directional I O pin 24 25 P14 I O Bi direc...

Страница 5: ...80H to FFH are indirectly addressable only 3 The Special Function Registers SFR addresses 80H to FFH are directly addressable only The Upper 128 bytes of RAM occupy the same address space as SFR but t...

Страница 6: ...WK7 P3WK6 P3WK5 P3WK4 P3WK3 P3WK2 P3WK1 P3WK0 00A6H P4WK 00000000B R W 0 P4WK6 P4WK5 0 0 0 0 0 009AH P0CON 00000000B R W P0CON7 P0CON6 P0CON5 P0CON4 P0CON3 P0CON2 P0CON1 P0CON0 009BH P1CON 00000000B R...

Страница 7: ...Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00F2H DADDR 00H R W 0 DA6 DA5 DA4 DA3 DA2 DA1 DA0 00F3H DFC 01H R W PULL_UP USB_CON FW_K RSU_SEL USBEN 0 ERWUP VPCON 00EAH TXDAT0 XXH W T07 T06 T05 T04 T03 T02 T01...

Страница 8: ...alling Edge 000BH Base Timer0 IE 1 T0 Base Timer0 Interrupt 0013H Reserved 001BH Base Timer1 IE 3 T1 Base Timer1 Interrupt 0023H Time Capture Interrupt0 IE 4 TC0 Time Capture0 Interrupt 002BH Reserved...

Страница 9: ...redictable data while write accesses will have no effect on the chip SFR Map for SH61F83 F8H FFH F0H B DADDR DFC XPAGE F7H E8H CRWCON TXDAT0 TXCNT0 TXFLG0 RXDAT0 RXCNT0 RXFLG0 EFH E0H ACC TXDAT1 TXCNT...

Страница 10: ...working bank RS1 RS0 00 Bank 0 Address 00H 07H 01 Bank 1 Address 08H 0FH 10 Bank 2 Address 10H 17H 11 Bank 3 Address 18H 1FH Bit 3 RS0 Bit 2 OV Overflow Flag Bit 1 X User definable flag Bit 0 P Parit...

Страница 11: ...crement reg Ri 1 3 Decrement indir byte direct 2 3 Decrement dir byte MUL AB 1 11 Multiply A and B 8 bit 1 20 Multiply AUXC A and B 16 bit DIV AB 1 11 Divide A by B 8 bit 1 20 Divide AUXC A by B 16 bi...

Страница 12: ...3 3 Load data pointer with 16 bit constant MOVC A A DPTR 1 7 Move code byte relative to DPTR to acc A A PC 1 8 Move code byte relative to PC to acc MOVX Ri A 1 4 Move acc to xdata byte 8 bit address...

Страница 13: ...ve address ACALL addr11 2 7 Absolute subroutine call LCALL addr16 3 7 Long subroutine call RET 1 8 Return from subroutine RETI 1 8 Return from interrupt AJMP addr11 2 4 Absolute jump LJMP addr16 3 5 L...

Страница 14: ...ole chip This process is fulfilled by a power on reset circuit and an auxiliary Lower voltage reset circuit LVRA monitoring VDD Once VDD climb up from 0V and cross the VPOR the internal POR signal wil...

Страница 15: ...the 1 8V regulator output voltage to the MCU core LVR1 reset signal will active when the input power of MCU core was less than VLVR1 and lasts for TPW LVR1 LVR1 signal will end after TRST LVR when the...

Страница 16: ...min 2 2V VLVR2 typ 2 4V and VLVR2 max 2 6V TPW LVR2 Drop Down Pulse Width for LVR2 2 9 X TSYS TRST LVR Internal Low voltage Reset Hold Time 2 16 X TSYS 5 1 3 External Reset 1 Normal mode and IDLE mode...

Страница 17: ...DT reset Resume reset Note1 The new Pre scalar value will be loaded after the Watchdog Timer was cleared write 55H to CLRWDT register Note2 When system enters Power Down Mode WDT will stop due to the...

Страница 18: ...me as standard 8051 micro controller The interrupt will be serviced and following RETI the next instruction to be executed will be the one following the instruction that put the device into IDLE mode...

Страница 19: ...me Enable Register Bit 7 0 P3WK 7 0 00h R W 1 Enable wake up function of PORT3 s pins Low level trigger 0 Disable wake up function of PORT3 s pins Low level trigger Reset source Hardware reset 00A6H P...

Страница 20: ...se a resume reset 2 Wake up Timer time out 3 USB Bus Non idle State VDM is low or VDM VDP both high Note1 In the case that the Wake up Timer wakes up from Power down mode there should be at least 32uS...

Страница 21: ...ORT0 MOV P0WK 00H Disable PORT0 resume ability ORL DFC 10H RSU_SEL 1 FW issue K State ORL DFC 02H ERWUP 1 Enable Remote Wake Up function MOV CLRWDT 55H Clear Watch Dog Timer ORL PCON 02H Set POWER DOW...

Страница 22: ...Time Out Waveform USB Bus Non idle State Resume Reset Resume reset after Non idle event Power down Mode Non idle event Reset 2 7ms Figure 5 10 USB Non idle Resume Reset Waveform USB reset signal at Po...

Страница 23: ...9 TRING 16ms 32KHz 1001 2 10 TRING 32ms 32KHz 1010 211 TRING 64ms 32KHz 1011 2 12 TRING 128ms 32KHz 1000 213 TRING 256ms 32KHz 1101 2 14 TRING 512ms 32KHz 1110 215 TRING 1 024s 32KHz 1111 2 16 TRING 2...

Страница 24: ...h H W Reset Source Clear Register with Resume Source Is wake up event Yes No Is Portx Resume event 2 7ms Reset Hold Time Is LVR event Is WKT Time out event 10 9ms Reset Hold Time Period 1 0 Reset Hold...

Страница 25: ...ure Control Bits Description P2 x P2CON x Port2 7 0 Port2 I O Shown in Figure 6 1 0 0 Output Low 0 4V min 4mA 1 0 Output High 2 4V min 50uA I X 1 HI Z 6 4 Port 3 Configuration Reset source Hardware re...

Страница 26: ...SH61F83 26 Figure 6 1 PORT Configuration 1 Input Select 1 0 Output Data I O Port Reg Read in Data Disable Output Port PnSELx Weakly Pull Up Weakly Pull Up Figure 6 2 PORT Configuration 2...

Страница 27: ...Figure 6 3 for the general circuit diagram Note 2 When entering USB Mode USB_CON 1 or P46 Output Mode P4CON6 0 PULL_UP function will be controlled by H W automatically regardless of the value in the...

Страница 28: ...USB reset or WDT reset Bit6 0b Reserved Bit5 0b Reserved Bit4 ETC0 0b R W Time Capture0 interrupt Bit3 ET1 0b R W Base Timer1 interrupt Bit2 0b Reserved Bit1 ET0 0b R W Base Timer0 interrupt Bit0 EEXT...

Страница 29: ...NAKT0 0b R W T0 NAK interrupt Enable bit 1 enables the interrupt Enable bit 0 disables the interrupt Reset Source Hardware reset or USB reset 00DDH IRQEN2 Initial Value FUN Interrupt Enable Register B...

Страница 30: ...nterrupt Event IE ETC0 0023H ENAKT0 ENAKR0 ENAK1 ENAK2 ET0STL ER0STL EIN1 EIN2 IRQEN ESUSP EOVL IRQEN2 ESTUP 0043H EOWSTUP 004BH EOT0ERR 0053H EIN0 005BH EOUT0 0063H ESIE 006BH EFUN 0073H IE2 TC0F_INT...

Страница 31: ...higher priority level already in progress The hardware generated LCALL accesses the contents of the Program Counter pushed onto the stack and reloads the PC with the beginning address of the service r...

Страница 32: ...0 to clear write 1 no effect Reset Source Hardware reset or USB reset Bit5 SIE 0b R W When OUT0 IN0 IN1 or IN2 is responded by a NAK responds ACK to IN1 IN2 or responds STALL to IN0 or OUT0 tokens SI...

Страница 33: ...effect Reset Source Hardware reset or USB reset Bit2 NAK1 0b R W When IN1 is responded by a NAK NAK1 will be set Write 0 to clear write 1 no effect Reset Source Hardware reset or USB reset Bit1 NAKR0...

Страница 34: ...n BTx register The input clock source of Base Timer x is controlled by the BTxM 2 0 register The following table shows 8 ranges of the Base Timer x For counting accuracy please set the Base Timer x re...

Страница 35: ...register Reset Source Hardware reset or USB reset 00C8H TCSTU Initial Value Time Capture Status register Bit 7 5 000b Reserved Bit4 TC0_OVL 0b R W Time Capture 0 TCAP0 Over Flow flag TC0_OVL event wil...

Страница 36: ...ad will cause an ETC0 IRQ Reset Source Hardware reset or USB reset Bit0 TC0R_INT 0b R W Enable Time Capture 0 rising edge interrupt request When ETC0 1 TC0R_INT 1 the rising edge on TC0 pad will cause...

Страница 37: ...E6 F W read TCAP0R TCAP0F register TC_CLREN 0 EA 1 ETC0 1 TC0F_INT 0 TC0R_INT 1 DB DC DD DE DF E0 E1 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF CF Figure 9 2 Timing Diagram of TC0 1 8 bit Free Run Counter...

Страница 38: ...01 02 03 04 05 CF 00 01 02 03 04 05 00 06 07 TC0_OVL Figure 9 4 Timing Diagram of TC0 3 8 bit Free Run Counter TC0 Input TCAP0R Register D0 D1 D3 00 01 02 03 04 05 06 TCAP0F Register TC0R_FULL TC0F_FU...

Страница 39: ...ME by issuing K state 1 Disable HW to response RESUME by issuing K state Reset Source Hardware reset or USB reset Bit3 USBEN 0B R W After power on USBEN is reset to 0 USBEN will be set to 1 after HOST...

Страница 40: ...B W TX FIFO 0 Transmit Bytes Count Reset Source no reset source 00E3H TXCNT1 Initial Value USB TX FIFO 1 Bytes Count Register Bit 7 4 0000B Reserved Bit 3 0 TXCNT1 3 0 XXXXB W TX FIFO 1 Transmit Bytes...

Страница 41: ...ointer Clear to 0 by H W after receiving ACK form host 0 Empty 1 Full Reset Source Hardware reset USB reset 00E7H TXFLG2 Initial Value USB TX FIFO 2 Flag Control Register Bit 7 4 0000B Reserved Bit3 T...

Страница 42: ...set TXCNTx bytes count set TxFULL 1 Receives ACK from HOST NO YES Firmware Process note The F W must check the corresponding TxFULL bit which is empty at first when it wants to write up data to the TX...

Страница 43: ...reset or USB reset Bit1 STLR0 0B R W Pipe 0 stall bits STLR0 bit is used to stall the pipe 0 OUT token 0 responds ACK NAK or not respond to OUT token 1 SIE will respond STALL to HOST OUT token Reset...

Страница 44: ...under EP0 Control Read Write Transfer The RX FIFO operational model refers to Figure 10 2 In the following the related F W procedures and H W actions are described 1 After Hardware Reset or USB Reset...

Страница 45: ...300K 300K VBUS D D GND GND 5V USB ISP Boot Circuit Figure 11 1 2 Connect the Device USB Cable to the Boot Circuit D D being connected and then supply 5V power PC USB Cable or Power Supply 3 After LED...

Страница 46: ...SetUp 0x21 0x09 0x05 0x03 0x00 or 0x01 0x00 0x06 0x00 Out 0x05 0x75 0x00 0x00 0x00 0x00 In Data Length 0 User Program should run CLR IE 7 MOV A 05Ah MOV B 0A5h LJMP 0x3F00 2 After USB Cable being con...

Страница 47: ...sable Regulator 3 3V Regulator Voltage V33 V33 3 3 V VDD 4 4V 5 25V IO 20mA max 1 8V Regulator Voltage V18 1 7 1 8 1 9 V VDD 4 4V 5 25V IO 10mA max GPIO and LED Port Output High Voltage Port0 VOH1 2 4...

Страница 48: ...SYS FSYS 6MHz Power On Reset time TRST POR 2 16 TSYS FSYS 6MHz Low Voltage Reset time TRST LVR 2 16 TSYS FSYS 6MHz Drop Down Width for LVR1 TPW LVR1 2 9 TSYS FSYS 6MHz Drop Down Width for LVR2 TPW LVR...

Страница 49: ...MIN TYP MAX UNIT CONDITIONS Input High Voltage Driven VIH USB 2 0 V DM DP Input High Voltage Floating VIHZ USB 2 7 3 6 V DM DP Input Low Voltage VIO USB 0 8 V DM DP Differential Input Sensitivity VDI...

Страница 50: ...My Computer P32 RSTB P20 P21 P22 P23 P24 P25 P26 P27 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P30 P31 R U I F3 T Y D F J K F4 G H F6 C V M B N F2 5 6 8 7 4 3 E K133 K56 O 7 Home...

Страница 51: ...SH61F83 51 Ordering Information Part No Package SH61F83H HAxxx Chip Form SH61F83Q 048QR HAxxx QFN48 6 X 6 Note xxx is the code number assigned by Sinowealth...

Страница 52: ...SH61F83 52 Package Information QFN 48L 6 X 6 Outline Dimensions unit inches mm...

Страница 53: ...ng to frame 33 PORT2 3 674 32 331 63 32 8 PORT3 5 674 32 278 1 7 34 PORT2 4 674 32 412 63 33 9 PORT3 6 674 32 359 1 8 35 PORT2 5 674 32 493 63 34 10 PORT3 7 674 32 472 05 9 36 PORT2 6 674 32 574 63 35...

Страница 54: ...SH61F83 54 Data Sheet Revision History Revision No History Date 2 0 Add notice P20 P39 Feb 2018 1 0 Original Jun 2013...

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