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SH61F83
19
00A2H
P0WK
Initial Value
Port0 Resume Enable Register
Bit[7:0] P0WK[7:0]
00h
R/W
1: Enable wake-up function of PORT0’s pins (Low level trigger)
0: Disable wake-up function of PORT0’s pins (Low level trigger)
Reset source: Hardware reset
00A3H
P1WK
Initial Value
Port1 Resume Enable Register
Bit[7:0] P1WK[7:0]
00h
R/W
1: Enable wake-up function of PORT1’s pins (Low level trigger)
0: Disable wake-up function of PORT1’s pins (Low level trigger)
Reset source: Hardware reset
00A4H
P2WK
Initial Value
Port2 Resume Enable Register
Bit[7:0] P2WK[7:0]
00h
R/W
1: Enable wake-up function of PORT2’s pins (Low level trigger)
0: Disable wake-up function of PORT2’s pins (Low level trigger)
Reset source: Hardware reset
00A5H
P3WK
Initial Value
Port3 Resume Enable Register
Bit[7:0] P3WK[7:0]
00h
R/W
1: Enable wake-up function of PORT3’s pins (Low level trigger)
0: Disable wake-up function of PORT3’s pins (Low level trigger)
Reset source: Hardware reset
00A6H
P4WK
Initial Value
Port4 Resume Enable Register
Bit7
-
0b
-
Reserved
Bit[6:5] P4WK[6:5]
00b
R/W
1: Enable wake-up function of PORT4’s pins (Low level trigger)
0: Disable wake-up function of PORT4’s pins (Low level trigger)
Reset source: Hardware reset
Bit[4:0]
-
00000b
-
Reserved
In this example, Watch-dog Timer can be cleared either before entering IDLE mode or after terminating IDLE mode. The
number of NOPs applied after the instruction that put the device into IDLE mode depends on the type of the instruction in order
to make the program work properly. In INTSUB, it detects if interrupts occur in Idle mode or not.
:
:
:
IDLE:
MOV
CLRWDT, #55H
ORL PCON, #01H
MOV SUSLO, #55H
NOP
NOP
NOP
MOV CLRWDT, #55H
:
:
INTSUB:
:
MOV
A, MD_FG
ANL A, #08H
JZ
NORMAL:
RETI
NORMAL:
:
:
RETI