SH61F83
14
4. Oscillators
The SH61F83 has a built-in 6MHz RC resonator for system clock. The oscillator generates the system timing and control
signal to be supplied to the CPU core and the on-chip peripherals, such as USB, Timer and so on.
Besides, the SH61F83 also has a built-in 32KHz RC resonator to generate the clock for wake up timer.
5. Reset and Power-reducing Mode
There are totally four Reset Sources in the SH61F83 application.
Hardware reset: Low-Voltage Reset, Power-On Reset or External Reset
WDT (Watch-dog Timer) Reset
Resume Reset
USB Reset
5.1. Hardware Reset
5.1.1. Power-On Reset (POR) and LVRA
When power is first applied to the SH61F83, the internal Power-On Reset will be generated and reset the whole chip.
This process is fulfilled by a power-on reset circuit and an auxiliary Lower-voltage reset circuit (LVRA) monitoring V
DD
. Once
V
DD
climb up from 0V and cross the V
POR
, the internal POR signal will active and end after T
RST(POR)
.
The LVRA will perform as a function Low-voltage Reset when system is normal running (under normal/idle/power-down
mode). LVRA reset signal (this signal is shared with POR signal) will active when V
DD
was less than V
LVRA
and lasts for
T
PW(LVRA)
, LVRA signal will end after T
RST(LVR)
when V
DD
was larger than V
LVRA
.
See Figure5-1 for the POR and LVRA behavior.
MCU Reset
T
RST(POR)
V
DD
T
PW(LVRA)
T
RST(LVR)
V
LVRA
GND
V
POR
Figure 5-1. Power-on Reset and LVRA
Note:
V
POR(max.)
= 3.6V
V
LVRA(min.)
= 2.9V, V
LVRA(typ.)
= 3.0V, and V
LVRA(max.)
= 3.1V
T
PW(LVRA)
(Drop-Down Pulse Width for LVRA) = 2
9
X T
SYS
T
RST(POR)
(Internal Power-on Reset Hold Time) = 2
16
X
T
SYS
T
RST(LVR)
((Internal Low-voltage Reset Hold Time) = 2
16
X T
SYS
