SH61F83
42
The TX FIFO operational model refers to Figure10-1.
In the following, the related F/W procedures and H/W actions are described.
(1) After Hardware Reset or USB Reset, the
TxFULL
bit in
TXFLGx
will reset to 0 to announce no data in FIFOs (x = 0/1/2).
(2) F/W writes up to n bytes of data to the
TXDATx
FIFO. (n = 0-8)
(3) F/W writes data byte count to the corresponding
TXCNTx
register.
(4) F/W sets the
TxFULL
bit.
(5) SIE issues data from the corresponding FIFO byte-by-byte after SIE receives a valid corresponding IN transaction.
(6) SIE waits the ACK.
(7) After SIE receives ACK package successively, the
TxFULL
bit is then reset to 0 by H/W. If SIE don‘t receive ACK,
TxFULL
is on its original status.
Hardware Reset or
USB Reset
set TXDATx = NULL
set TxFULL = 0
Firmware Process
set TXDATx = TX data
set TXCNTx = bytes count
set TxFULL = 1
Receives ACK
from HOST ?
NO
YES
Firmware Process note:
The F/W must check the corresponding
TxFULL bit which is empty at first when it
wants to write up data to the TXDATx FIFO.
Hardware
Firmware
Figure 10-1. TX FIFO Operating Model (for a valid IN Transaction)
10.6. RXDAT0
USB Receive FIFO Data Register for Endpoint 0.SIE writes data to the RXDAT0 FIFO for Endpoint 0. CPU read data from the
RXDAT0 for Endpoint 0. The operational model refers to Figure 10-2.
00EDH
RXDAT0 Initial Value
USB RX FIFO 0 Data Register
Bit[7:0]
RXDAT0
[7:0]
XXH
R
RX FIFO Data Register for Endpoint 0
Reset Source: no reset source
10.7. RXCNT0
USB Received FIFO bytes count register for Endpoint 0. SIE writes the corresponding bytes count to this register after writing
data to the RXDAT0.
00EEH
RXCNT0 Initial Value
USB RX FIFO 0 Bytes Count Register
Bit[7:4]
-
0000B
-
Reserved
Bit[3:0]
RXCNT0
[3:0]
XXXXB
W
RX FIFO bytes count register for Endpoint 0
Reset Source: no reset source
