Silicon Laboratories SiM3L1xx, Руководство пользователя

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S i M 3 L 1 x x
Rev 1.1 17
Memory LDO Output Setting
5
V
LDOMEM
During Programming 1.8 — 1.9 V
During Normal
Operation
1.5 — 1.9 V
Digital LDO Output Setting V
LDODIG
F
AHB
< 20 MHz 1.0 — 1.9 V
F
AHB
> 20 MHz 1.2 — 1.9 V
Analog LDO Output Setting During
Normal Operation
6
V
LDOANA
1.8 V
Table 3.5. On-Chip Regulators (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1.
See reference manual for recommended inductors.
2.
Recommended: X7R or X5R ceramic capacitors with low ESR. Example: Murata GRM21BR71C225K with ESR < 10
m

(@ frequency > 1 MHz).
3.
Input voltage specification accounts for the internal LDO dropout voltage under the maximum load condition to ensure
that the LDO output voltage will remain at a valid level as long as
V
LDOIN
is at or above the specified minimum.
4.
The memory LDO output should always be set equal to or lower than the output of the analog LDO. When lowering both
LDOs (for example to go into PM8 under low supply conditions), first adjust the memory LDO and then the analog LDO.
When raising the output of both LDOs, adjust the analog LDO before adjusting the memory LDO.
5.
Output range represents the programmable output range, and does not reflect the minimum voltage under all
conditions. Dropout when the input supply is close to the output setting is normal, and accounted for.
6.
Analog peripheral specifications assume a 1.8 V output on the analog LDO.