Si4010-C2
38
Rev. 1.0
12.1. Register Description
SFR Address = 0xCE
XREG Address = 0x400C
SFR Definition 12.1. PA_LVL
Bit
7
6
5
4
3
2
1
0
Name
PA_LVL_NSLICE[4:0]
PA_LVL_BIAS[2:0]
Type
R/W
R/W
Reset
0
0
Bit
Name
Function
7:3
PA_LVL_
NSLICE
[4:0]
Number of Slices Enabled in the PA Driver.
This parameter determines the output current drive of the PA. Programming this
register directly is not recommended. Use the vPa_Setup() API function instead.
2:0
PA_LVL_
BIAS
[2:0]
PA Level Bias.
This parameter determines the bias current per slice of the PA. Programming this
register directly is not recommended. Use the vPa_Setup() API function instead.
XREG Definition 12.2. wPA_CAP
Byte
Offset
1
0
Name
PA_CAP[1:0]
Type
R/W
Reset
0x00
0x00
Bit
Name
Function
1:0
PA_CAP
[1:0]
PA Variable Capacitance.
9-bit linear control value of the output capacitance of the PA. Accessed as 2 bytes
(word) in big-endian fashion. Upper bits [15:9] are read as 0. Range: 2.4–12.5 pF (not
exact values). The resonance frequency and impedance matching between the PA
output and the connected antenna can be tuned by changing this value. This register
is set by the Power Amplifier Module API.