Silicon Laboratories Si4010-C2, Руководство пользователя

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Si4010-C2
122 Rev. 1.0
SFR Address = 0xB6
SFR Definition 30.7. PORT_SET
Bit 7 6 5 4 3 2 1 0
Name
EDGE_
INT1
EDGE_
INT0
PORT_CLKOUT[1:0] PORT_
CLKEN PORT_
REFEN
Reserved Reserved
Type
R/W R/W R/W R/W R/W R/W R/W R/W
Reset
0 0 0 0 0 0 0 0
Bit Name Function
7
EDGE_
INT1
Edge Control for INT1.
This bit controls whether single edge or both edges invoke the interrupt.
0: Single edge, polarity specified by NEG_INT1 in PORT_INTCFG.
1: Both edges, which means any edge, invoke INT1 interrupt.
6
EDGE_
INT0
Edge Control for INT0.
This bit controls whether single edge or both edges invoke the interrupt.
0: Single edge, polarity specified by NEG_INT0 in PORT_INTCFG.
1: Both edges, which means any edge, invoke INT0 interrupt.
5:4
PORT_
CLKOUT
[1:0]
Select which GPIO Pin is used as Clock Output Pin.
PORT_CLKOUT[0]: 1 .. clk output at GPIO[4], 0 .. normal/other GPIO[4] operation
PORT_CLKOUT[1]: 1 .. clk output at GPIO[6], 0 .. normal/other GPIO[6] operation
Both outputs can be used simultaneously. The actual clock waveform can be
enabled/disabled by port_clken bit, but the GPIO configuration is purely controlled by
PORT_CLKOUT.
3
PORT_
CLKEN
Enable Output Clock, Which is Possibly Coming out on GPIO[4] and/or
GPIO[6].
This bit is just a clock enable/disable, it does not configure the GPIO for clock out-
puts. The port configuration must be done by port_clkout below. The generated clock
division is controlled by CLKOUT_SET register. If the clock is disabled by
PORT_CLKEN=0 the current period in progress will be finished and the output clock
will stop as logic 0.
2
PORT_
REFEN
Enable CLK_REF Reference Clock to come from GPIO[3].
The GPIO[3] pad is forced to be an input. There is not need to change p0 or p0con
register values, since port_refen has higher priority.
1:0 Reserved These bits must be left at 0.