Si4010-C2
48
Rev. 1.0
SFR Address = 0xBE
SFR Definition 15.2. SYSGEN
Bit
7
6
5
4
3
2
1
0
Name
SYSGEN_
SHUT-
DOWN
Re-served PWR_1ST
_TIME
RTC_
TICKCLR
PORT_
HOLD
SYSGEN_DIV[2:0]
Type
R/W
R
R
W
R/W
R/W
Reset
0
0
—
0
0
0
0
0
Bit
Name
Function
7
SYSGEN_
SHUT-
DOWN
System General Shutdown.
Setting this bit causes shutdown of MCU and most analog. Recovery from this is via
falling edge on any GPIO, which results in a power up and a power on reset. This is
THE bit that shuts down the power to nearly everything.
0: Normal operation
1: Shutdown. Do not use this bit directly. It is recommended to use the
vSys_Shutdown() API call.
6
Reserved
Read as 0. Write has no effect.
5
PWR_1ST_
TIME
Initial Powerup Indicator.
Read only register. It will get set when power up was caused by a battery insertion.
4
RTC_
TICKCLR
Real Time Clock Clear.
0: Normal operation
1: Clears the real time clock 5.12us counter.
3
PORT_
HOLD
Port Hold.
This bit needs to be set before shutting down, it delays any button pushes that occur
between this bit setting and shutdown until the chip completes shutdown, to ensure
the shutdown process cannot be interrupted.
0: Normal operation
1: Holds GPIO port values until shutdown is complete
2:0
SYSGEN_
DIV[2:0]
System Clock Generator Divider.
System clock divider control to generate the system clock.
000: 24 MHz; div = 1
001: 12 MHz; div = 2
010: 6.0 MHz; div = 4
011: 3.0 MHz; div = 8
100: 1.5 MHz; div = 16
101: 0.75 MHz; div = 32
110: 0.375 MHz; div = 64
111: 0.1875 MHz; div = 128
